데이터 시트차례Processor Extension Pak and Header Specification1Processor Extension Pak and Header Defined1Why Do I Need A Header To Debug?2Debug Details3Programming Details4General Header Setup4Device vs. Optional Header Features6MPLAB IDE and MPLAB X IDE Use with Headers7Calibration Bits7Performance Issues7Related Debug Tools7Customer Support8Required Debug Headers9Introduction9AC162050, AC16205811AC162052, AC162055, AC162056, AC16205713AC162053, AC16205415AC162059, AC162070, AC16209617AC16206019AC16206121AC16206623AC16208325AC244023, AC24402428AC24402830AC24404532AC244051, AC24405234Optional Debug Headers37Introduction37AC162062, AC162079, AC162087, AC16209141AC16206443AC162065, AC24402245AC162067, AC16207448AC16207851AC162088, AC16209454AC244026, AC24402757AC244033, AC24403460AC244035, AC24403662AC244043, AC24404464AC244046, AC24404766AC244053, AC24405468Debug Header Target Footprints71Introduction71DIP Device Footprints71TQFP/PLCC Device Footprints71Debug Header Connections75Introduction756-Pin Modular Connector758-Pin SIL Connector766-Pin SIL Connector77SIL Optional Connection78Modular-to-SIL Adapter78Ordering Information79Appendix C: Revision History81Index83Worldwide Sales and Service88크기: 1.22메가바이트페이지: 88Language: English매뉴얼 열기
데이터 시트차례Devices Included In This Data Sheet:3High-Performance RISC CPU:3Special Microcontroller Features:3Extreme Low-Power Management PIC16LF72X with nanoWatt XLP:3Analog Features:3Peripheral Highlights:3Pin Diagrams – 28-Pin PDIP/SOIC/SSOP/QFN/UQFN (PIC16F722/723/726/PIC16LF722/723/726)5TABLE 1: 28-Pin PDIP/SOIC/SSOP/QFN/UQFN Summary (PIC16F722/723/726/PIC16LF722/723/726)6Pin Diagrams – 40-Pin PDIP (PIC16F724/727/PIC16LF724/727)7Pin Diagrams – 44-Pin TQFP (PIC16F724/727/PIC16LF724/727)8Pin Diagrams – 44-Pin QFN (PIC16F724/727/PIC16LF724/727)9TABLE 2: 40/44-Pin PDIP/tqfp/qfn Summary (PIC16F724/727/PIC16LF724/727)10Most Current Data Sheet12Errata12Customer Notification System121.0 Device Overview13FIGURE 1-1: PIC16F722/723/726/PIC16LF722/723/726 Block Diagram14FIGURE 1-2: PIC16F724/727/PIC16LF724/727 Block Diagram15TABLE 1-1: PIC16F72X/PIC16LF72X Pinout Description162.0 Memory Organization192.1 Program Memory Organization19FIGURE 2-1: Program Memory Map And Stack For The PIC16F722/LF72219FIGURE 2-2: Program Memory Map And Stack For The PIC16F723/LF723 and PIC16F724/LF72419FIGURE 2-3: Program Memory Map And Stack For The PIC16F726/LF726 and PIC16F727/LF727202.2 Data Memory Organization202.2.1 General Purpose Register File202.2.2 Special FUNCTION Registers20FIGURE 2-4: PIC16F722/LF722 Special Function Registers21FIGURE 2-5: PIC16F723/LF723 and PIC16F724/LF724 Special Function Registers22FIGURE 2-6: PIC16F726/LF726 and PIC16F727/LF727 Special Function Registers23TABLE 2-1: PIC16F72X/PIC16LF72X Special Function Register Summary24Register 2-1: STATUS: STATUS Register27Register 2-2: OPTION_REG: OPTION Register28Register 2-3: PCON: Power Control Register292.3 PCL and PCLATH30FIGURE 2-7: Loading Of PC In Different Situations302.3.1 computed goto302.3.2 Stack302.4 Program Memory Paging30EXAMPLE 2-1: Call of a Subroutine in Page 1 from Page 0302.5 Indirect Addressing, INDF and FSR Registers31EXAMPLE 2-2: Indirect Addressing31FIGURE 2-8: Direct/Indirect Addressing313.0 Resets33FIGURE 3-1: Simplified Block Diagram Of On-Chip Reset Circuit333.1 MCLR35FIGURE 3-2: Recommended MCLR Circuit353.2 Power-on Reset (POR)353.3 Power-up Timer (PWRT)353.4 Watchdog Timer (WDT)353.4.1 WDT Oscillator353.4.2 WDT Control36TABLE 3-1: WDT Status363.5 Brown-Out Reset (BOR)37FIGURE 3-3: Brown-Out Situations373.6 Time-out Sequence383.7 Power Control (PCON) Register38TABLE 3-2: Time-Out In Various Situations38TABLE 3-3: Reset Bits And Their Significance38FIGURE 3-4: Time-Out Sequence On Power-Up (Delayed MCLR): Case 139FIGURE 3-5: Time-Out Sequence On Power-Up (Delayed MCLR): Case 239FIGURE 3-6: Time-Out Sequence On Power-Up (MCLR With Vdd): Case 339TABLE 3-4: Initialization Condition for Registers40TABLE 3-5: Initialization Condition For Special Registers42TABLE 3-6: Summary Of Registers Associated With Resets424.0 Interrupts43FIGURE 4-1: Interrupt Logic434.1 Operation444.2 Interrupt Latency44FIGURE 4-2: INT Pin Interrupt Timing444.3 Interrupts During Sleep454.4 INT Pin454.5 Context Saving45EXAMPLE 4-1: Saving W, STATUS and PCLATH Registers in RAM454.5.1 INTCON Register46Register 4-1: INTCON: Interrupt Control Register464.5.2 PIE1 Register47Register 4-2: PIE1: Peripheral Interrupt Enable Register 1474.5.3 PIE2 Register48Register 4-3: PIE2: Peripheral Interrupt Enable Register 2484.5.4 PIR1 Register49Register 4-4: PIR1: Peripheral Interrupt Request Register 1494.5.5 PIR2 Register50Register 4-5: PIR2: Peripheral Interrupt Request Register 250TABLE 4-1: Summary of Registers Associated with Interrupts505.0 Low Dropout (LDO) Voltage Regulator516.0 I/O Ports536.1 Alternate Pin Function53Register 6-1: APFCON: Alternate Pin Function COntrol Register536.2 PORTA and the TRISA Registers54EXAMPLE 6-1: Initializing PORTA54Register 6-2: PORTA: PORTA Register54Register 6-3: TRISA: PORTA Tri-State Register546.2.1 ANSELA Register55Register 6-4: ANSELA: PORTA Analog Select Register556.2.2 Pin Descriptions and Diagrams56FIGURE 6-1: Block Diagram of RA057FIGURE 6-2: RA<3:1> Block Diagram58FIGURE 6-3: Block Diagram of RA458FIGURE 6-4: Block Diagram of RA559FIGURE 6-5: Block Diagram of RA660FIGURE 6-6: Block Diagram of RA760TABLE 6-1: Summary of Registers Associated with PORTA616.3 PORTB and TRISB Registers62EXAMPLE 6-2: Initializing PORTB626.3.1 ANSELB Register626.3.2 Weak Pull-Ups626.3.3 Interrupt-on-Change62Register 6-5: PORTB: PORTB Register63Register 6-6: TRISB: PORTB Tri-State Register63Register 6-7: WPUB: WEAK PULL-uP PORTB REGISTER64Register 6-8: IOCB: Interrupt-on-change PORTB Register64Register 6-9: ANSELB: PORTB Analog Select Register646.3.4 Pin Descriptions and Diagrams65FIGURE 6-7: Block Diagram of RB066FIGURE 6-8: Block Diagram of RB4, RB<2:1>67FIGURE 6-9: Block Diagram of RB368FIGURE 6-10: Block Diagram of rb569FIGURE 6-11: Block Diagram of RB670FIGURE 6-12: Block Diagram of RB771TABLE 6-2: Summary of Registers Associated with PORTB726.4 PORTC and TRISC Registers73EXAMPLE 6-3: Initializing PORTC73Register 6-10: PORTC: PORTC Register73Register 6-11: TRISC: PORTC Tri-State Register736.4.1 RC0/T1OSO/T1CKI746.4.2 RC1/T1OSi/CCP2746.4.3 RC2/CCP1746.4.4 RC3/SCK/SCL746.4.5 RC4/SDI/SDA746.4.6 RC5/SDO746.4.7 RC6/TX/CK746.4.8 RC7/RX/DT74FIGURE 6-13: Block Diagram of RC075FIGURE 6-14: Block Diagram of RC175FIGURE 6-15: Block Diagram of RC276FIGURE 6-16: Block Diagram of RC376FIGURE 6-17: Block Diagram of RC477FIGURE 6-18: Block Diagram of RC577FIGURE 6-19: Block Diagram of RC678FIGURE 6-20: Block Diagram of RC778TABLE 6-3: Summary of Registers Associated with PORTC796.5 PORTD and TRISD Registers80EXAMPLE 6-4: Initializing PORTD806.5.1 ANSELD Register80Register 6-12: PORTD: PORTD Register(1)80Register 6-13: TRISD: PORTD Tri-State Register(1)81Register 6-14: ANSELD: PORTD Analog Select Register(2)816.5.2 RD0/CPS8826.5.3 RD1/CPS9826.5.4 RD2/CPS10826.5.5 RD3/CPS11826.5.6 RD4/CPS12826.5.7 RD5/CPS13826.5.8 RD6/CPS14826.5.9 RD7/CPS1582FIGURE 6-21: Block Diagram of RD<7:0>82TABLE 6-4: Summary of Registers Associated with PORTD(1)836.6 PORTE and TRISE Registers84EXAMPLE 6-5: Initializing PORTE84Register 6-15: PORTE: PORTE Register85Register 6-16: TRISE: PORTE Tri-State Register85Register 6-17: ANSELE: PORTE Analog Select Register86TABLE 6-5: Summary of Registers Associated with PORTE866.6.1 RE0/AN5(1)876.6.2 RE1/AN6(1)876.6.3 RE2/AN7(1)876.6.4 RE3/MCLR/Vpp87FIGURE 6-22: Block Diagram of RE<2:0>88FIGURE 6-23: Block Diagram of RE3887.0 Oscillator Module897.1 Overview89FIGURE 7-1: Simplified PIC® MCU Clock Source Block Diagram897.2 Clock Source Modes907.3 Internal Clock Modes907.3.1 INTOSC and INTOSCIO Modes907.3.2 Frequency Select Bits (IRCF)907.4 Oscillator Control91Register 7-1: OSCCON: Oscillator Control Register917.5 Oscillator Tuning92Register 7-2: OSCTUNE: Oscillator Tuning ReGister927.6 External Clock Modes937.6.1 Oscillator Start-up Timer (OST)937.6.2 EC Mode93FIGURE 7-2: External Clock (EC) Mode Operation937.6.3 LP, XT, HS Modes93FIGURE 7-3: Quartz Crystal Operation (LP, XT or HS Mode)93FIGURE 7-4: Ceramic Resonator Operation (XT or HS Mode)947.6.4 External RC Modes94FIGURE 7-5: External RC Modes94TABLE 7-1: Summary of Registers Associated with Clock Sources948.0 Device Configuration958.1 Configuration Words95Register 8-1: CONFIG1: Configuration Word Register 195Register 8-2: CONFIG2: Configuration Word Register 2968.2 Code Protection978.3 User ID979.0 Analog-to-Digital Converter (ADC) Module99FIGURE 9-1: ADC Block Diagram999.1 ADC Configuration1009.1.1 Port Configuration1009.1.2 Channel Selection1009.1.3 ADC Voltage Reference1009.1.4 Conversion Clock100TABLE 9-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies101FIGURE 9-2: Analog-to-Digital Conversion Tad Cycles1019.1.5 Interrupts1029.2 ADC Operation1029.2.1 Starting a Conversion1029.2.2 Completion of a Conversion1029.2.3 Terminating a conversion1029.2.4 ADC Operation During Sleep1029.2.5 Special Event Trigger1029.2.6 A/D Conversion Procedure103EXAMPLE 9-1: A/D Conversion1039.2.7 ADC Register Definitions104Register 9-1: ADCON0: A/D Control Register 0104Register 9-2: ADCON1: A/D Control Register 1105Register 9-3: ADRES: ADC Result Register1059.3 A/D Acquisition Requirements106EQUATION 9-1: Acquisition Time Example106FIGURE 9-3: Analog Input Model107FIGURE 9-4: ADC Transfer Function107TABLE 9-2: Summary of Associated ADC Registers10810.0 Fixed Voltage Reference109Register 10-1: FVRCON: Fixed Voltage Reference Register10911.0 Timer0 Module11111.1 Timer0 Operation11111.1.1 8-bit Timer mode11111.1.2 8-Bit Counter Mode111FIGURE 11-1: Block Diagram of the Timer0/WDT Prescaler11111.1.3 Software Programmable Prescaler11211.1.4 Timer0 Interrupt11211.1.5 8-BIT COUNTER MODE SYNCHRONIZATION112Register 11-1: OPTION_REG: OPTION Register113TABLE 11-1: Summary of Registers Associated with Timer011312.0 Timer1 Module with Gate Control115FIGURE 12-1: Timer1 Block Diagram11512.1 Timer1 Operation116TABLE 12-1: Timer1 Enable Selections11612.2 Clock Source Selection11612.2.1 Internal Clock Source11612.2.2 External Clock Source116TABLE 12-2: Clock Source Selections11612.3 Timer1 Prescaler11712.4 Timer1 Oscillator11712.5 Timer1 Operation in Asynchronous Counter Mode11712.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode11712.6 Timer1 Gate11812.6.1 Timer1 Gate Count Enable118TABLE 12-3: Timer1 Gate Enable Selections11812.6.2 Timer1 Gate Source Selection118TABLE 12-4: Timer1 Gate Sources118TABLE 12-5: WDT/Timer1 Gate Interaction11912.6.3 Timer1 Gate Toggle Mode11912.6.4 Timer1 Gate Single-Pulse Mode11912.6.5 Timer1 Gate Value Status11912.6.6 Timer1 Gate Event Interrupt11912.7 Timer1 Interrupt12012.8 Timer1 Operation During Sleep12012.9 CCP Capture/Compare Time Base12012.10 CCP Special Event Trigger120FIGURE 12-2: Timer1 Incrementing Edge120FIGURE 12-3: Timer1 Gate Count Enable Mode121FIGURE 12-4: Timer1 Gate Toggle Mode121FIGURE 12-5: Timer1 Gate Single-Pulse Mode122FIGURE 12-6: Timer1 Gate Single-Pulse and Toggle Combined Mode12312.11 Timer1 Control Register124Register 12-1: T1CON: Timer1 Control Register12412.12 Timer1 Gate Control Register125Register 12-2: T1GCON: Timer1 Gate Control Register125TABLE 12-6: Summary of Registers Associated with Timer112613.0 Timer2 Module12713.1 Timer2 Operation127FIGURE 13-1: Timer2 Block Diagram127Register 13-1: T2CON: Timer2 Control Register128TABLE 13-1: Summary of Registers Associated With Timer212814.0 Capacitive Sensing Module129FIGURE 14-1: Capacitive Sensing Block Diagram12914.1 Analog MUX13014.2 Capacitive Sensing Oscillator13014.3 Timer resources13014.4 Fixed Time Base13014.4.1 Timer013014.4.2 Timer1130TABLE 14-1: TIMER1 ENABLE FUNCTION13014.5 Software Control13114.5.1 Nominal Frequency (No Capacitive Load)13114.5.2 Reduced Frequency (additional capacitive load)13114.5.3 Frequency threshold13114.6 Operation during Sleep132Register 14-1: CPSCON0: Capacitive Sensing Control Register 0133Register 14-2: CPSCON1: Capacitive Sensing Control Register 1134TABLE 14-2: Summary of Registers Associated with Capacitive Sensing13415.0 Capture/Compare/PWM (CCP) Module135TABLE 15-1: CCP Mode – Timer Resources Required135TABLE 15-2: Interaction of Two CCP Modules135Register 15-1: CCPxCON: CCPx Control Register13615.1 Capture Mode13715.1.1 CCPx pin Configuration137FIGURE 15-1: Capture Mode Operation Block Diagram13715.1.2 Timer1 Mode Selection13715.1.3 Software Interrupt13715.1.4 CCP Prescaler137EXAMPLE 15-1: Changing Between Capture Prescalers13715.1.5 Capture During Sleep137TABLE 15-3: Summary of Registers Associated with Capture13815.2 Compare Mode139FIGURE 15-2: Compare Mode Operation Block Diagram13915.2.1 CCPx Pin Configuration13915.2.2 timer1 Mode Selection13915.2.3 Software Interrupt Mode13915.2.4 Special Event Trigger13915.2.5 Compare During Sleep139TABLE 15-4: Summary of Registers Associated with Compare14015.3 PWM Mode141FIGURE 15-3: Simplified PWM Block Diagram141FIGURE 15-4: CCP PWM Output14115.3.1 CCPx Pin Configuration14115.3.2 PWM period142EQUATION 15-1: PWM Period14215.3.3 PWM Duty Cycle142EQUATION 15-2: Pulse Width142EQUATION 15-3: Duty Cycle Ratio14215.3.4 PWM Resolution143EQUATION 15-4: PWM Resolution143TABLE 15-5: Example PWM Frequencies and Resolutions (Fosc = 20 MHz)143TABLE 15-6: Example PWM Frequencies and Resolutions (Fosc = 8 MHz)14315.3.5 Operation in Sleep Mode14315.3.6 Changes in System Clock Frequency14315.3.7 Effects of Reset14315.3.8 Setup for PWM Operation143TABLE 15-7: Summary of Registers Associated with PWM14416.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART)145FIGURE 16-1: AUSART Transmit Block Diagram145FIGURE 16-2: AUSART Receive Block Diagram14616.1 AUSART Asynchronous Mode14716.1.1 AUSART Asynchronous Transmitter147FIGURE 16-3: Asynchronous Transmission148FIGURE 16-4: Asynchronous Transmission (Back-to-Back)148TABLE 16-1: Registers Associated with Asynchronous Transmission14916.1.2 AUSART Asynchronous Receiver150FIGURE 16-5: Asynchronous Reception152TABLE 16-2: Registers Associated with Asynchronous Reception153Register 16-1: TXSTA: Transmit STATUS AND CONTROL REGISTER154Register 16-2: RCSTA: Receive STATUS AND CONTROL REGISTER15516.2 AUSART Baud Rate Generator (BRG)156EXAMPLE 16-1: Calculating Baud Rate Error156TABLE 16-3: Baud Rate Formulas156TABLE 16-4: Registers Associated with the bAUD rATE gENERATOR156TABLE 16-5: BAUD Rates for Asynchronous Modes15716.3 AUSART Synchronous Mode15916.3.1 Synchronous Master Mode159FIGURE 16-6: Synchronous Transmission160FIGURE 16-7: Synchronous Transmission (Through TXEN)160TABLE 16-6: Registers Associated with Synchronous Master Transmission160FIGURE 16-8: Synchronous Reception (Master Mode, SREN)162TABLE 16-7: Registers Associated with Synchronous Master Reception16216.3.2 Synchronous slave Mode163TABLE 16-8: Registers Associated with Synchronous Slave Transmission163TABLE 16-9: Registers Associated with Synchronous Slave Reception16416.4 AUSART Operation During Sleep16516.4.1 Synchronous Receive During Sleep16516.4.2 Synchronous Transmit During Sleep16517.0 SSP Module Overview16717.1 SPI Mode167FIGURE 17-1: Typical SPI Master/Slave Connection167FIGURE 17-2: SPI Mode Block Diagram16817.1.1 Master Mode169FIGURE 17-3: SPI Master Mode Waveform170EXAMPLE 17-1: Loading the SSPBUF (SSPSR) Register17017.1.2 Slave Mode171FIGURE 17-4: SPI Mode Waveform (Slave Mode with CKE = 0)172FIGURE 17-5: SPI Mode Waveform (Slave Mode with CKE = 1)172FIGURE 17-6: Slave Select Synchronization Waveform173Register 17-1: SSPCON: Sync Serial Port Control Register (SPI Mode)174Register 17-2: SSPSTAT: Sync Serial Port Status Register (SPI Mode)175TABLE 17-1: Summary of Registers Associated with SPI Operation17617.2 I2C Mode177FIGURE 17-7: I2C™ Mode Block Diagram177FIGURE 17-8: Typical I2C™ Connections17717.2.1 Hardware Setup17717.2.2 Start and Stop Conditions178FIGURE 17-9: Start and Stop Conditions17817.2.3 Acknowledge178TABLE 17-2: Data Transfer Received Byte Actions17817.2.4 Addressing17917.2.5 Reception180FIGURE 17-10: I2C™ Waveforms for Reception (7-bit Address)180FIGURE 17-11: I2C™ Slave Mode Timing (Reception, 10-bit Address)18117.2.6 Transmission182FIGURE 17-12: I2C Waveforms for Transmission (7-bit Address)182FIGURE 17-13: I2C Slave Mode Timing (Transmission 10-bit Address)18317.2.7 Clock Stretching18417.2.8 Firmware Master Mode18417.2.9 Multi-Master Mode18417.2.10 Clock Synchronization18517.2.11 Sleep Operation185FIGURE 17-14: Clock Synchronization Timing185Register 17-3: SSPCON: Synchronous Serial Port Control Register (I2C Mode)186Register 17-4: SSPSTAT: Synchronous Serial Port Status Register (I2C Mode)187Register 17-5: SSPMSK: SSP Mask Register188Register 17-6: SSPADD: SSP I2C Address Register18818.0 Program Memory Read189EXAMPLE 18-1: PROGRAM Memory Read189Register 18-1: PMCON1: Program Memory Control 1 register190Register 18-2: PMDATH: Program Memory Data High register190Register 18-3: PMDATL: Program Memory Data Low register190Register 18-4: PMADRH: Program Memory Address High register191Register 18-5: PMADRL: Program Memory Address Low register191TABLE 18-1: Summary of Registers Associated with Program Memory Read19119.0 Power-Down Mode (Sleep)19319.1 Wake-up from Sleep19319.2 Wake-up Using Interrupts194FIGURE 19-1: Wake-Up From Sleep Through Interrupt194TABLE 19-1: Summary of Registers Associated with pOWER-dOWN mODE19420.0 In-Circuit Serial Programming™ (ICSP™)195FIGURE 20-1: Typical connection for ICSP™ programming19521.0 Instruction Set Summary19721.1 Read-Modify-Write Operations197TABLE 21-1: Opcode Field Descriptions197FIGURE 21-1: General Format for Instructions197TABLE 21-2: PIC16F72X/PIC16LF72X Instruction Set19821.2 Instruction Descriptions1991.0 Development Support20723.0 Electrical Specifications211Absolute Maximum Ratings(†)21123.1 DC Characteristics: PIC16F72X/PIC16LF72X-I/E (Industrial, Extended)212FIGURE 23-1: POR and POR Rearm with Slow Rising Vdd21323.2 DC Characteristics: PIC16F72X/PIC16LF72X-I/E (Industrial, Extended)21423.3 DC Characteristics: PIC16F72X/PIC16LF72X-I/E (Power-Down)21623.4 DC Characteristics: PIC16F72X/PIC16LF72X-I/E21823.5 Thermal Considerations22023.6 Timing Parameter Symbology221FIGURE 23-2: Load Conditions22123.7 AC Characteristics: PIC16F72X-I/E222FIGURE 23-3: Clock Timing222FIGURE 23-4: PIC16F72X Voltage Frequency Graph, -40°C £ Ta £ +125°C222FIGURE 23-5: PIC16LF72X Voltage Frequency Graph, -40°C £ Ta £ +125°C223FIGURE 23-6: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature223TABLE 23-1: Clock Oscillator Timing Requirements224TABLE 23-2: Oscillator Parameters225FIGURE 23-7: CLKOUT and I/O Timing225TABLE 23-3: CLKOUT and I/O Timing Parameters226FIGURE 23-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing226FIGURE 23-9: Brown-Out Reset Timing and Characteristics227TABLE 23-4: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and Brown-Out Reset Parameters228FIGURE 23-10: Timer0 and Timer1 External Clock Timings229TABLE 23-5: Timer0 and Timer1 External Clock Requirements229FIGURE 23-11: Capture/Compare/PWM Timings (CCP)230TABLE 23-6: Capture/Compare/PWM Requirements (CCP)230TABLE 23-7: PIC16F72X A/D Converter (ADC) Characteristics:230TABLE 23-8: PIC16F72X A/D Conversion Requirements231FIGURE 23-12: PIC16F72X A/D Conversion Timing (Normal Mode)231FIGURE 23-13: PIC16F72X A/D Conversion Timing (Sleep Mode)232FIGURE 23-14: USART Synchronous Transmission (Master/Slave) Timing232TABLE 23-9: USART Synchronous Transmission Requirements232FIGURE 23-15: USART Synchronous Receive (Master/Slave) Timing233TABLE 23-10: USART Synchronous Receive Requirements233FIGURE 23-16: SPI Master Mode Timing (CKE = 0, SMP = 0)234FIGURE 23-17: SPI Master Mode Timing (CKE = 1, SMP = 1)234FIGURE 23-18: SPI Slave Mode Timing (CKE = 0)235FIGURE 23-19: SPI Slave Mode Timing (CKE = 1)235TABLE 23-11: SPI Mode requirements236FIGURE 23-20: I2C™ Bus Start/Stop Bits Timing236TABLE 23-12: I2C™ Bus Start/Stop Bits Requirements237FIGURE 23-21: I2C™ Bus Data Timing237TABLE 23-13: I2C™ Bus Data Requirements238TABLE 23-14: Cap Sense Oscillator Specifications239FIGURE 23-22: Cap Sense Oscillator23924.0 DC and AC Characteristics Graphs and Charts241FIGURE 24-1: PIC16F72X Maximum Idd vs. Fosc over Vdd, EC Mode, Vcap = 0.1µF241FIGURE 24-2: PIC16LF72X Maximum Idd vs. Fosc over Vdd, EC Mode241FIGURE 24-3: PIC16F72X Typical Idd vs. Fosc Over Vdd, EC Mode, Vcap = 0.1µF242FIGURE 24-4: PIC16LF72X Typical Idd vs. Fosc over Vdd, EC Mode242FIGURE 24-5: PIC16F72X Maximum Idd vs. Vdd over Fosc, EXTRC Mode, Vcap = 0.1µF243FIGURE 24-6: PIC16LF72X Maximum Idd vs. Vdd over Fosc, EXTRC Mode243FIGURE 24-7: PIC16F72X Typical Idd vs. Vdd over Fosc, EXTRC Mode, Vcap = 0.1µF244FIGURE 24-8: PIC16LF72X Typical Idd vs. Vdd over Fosc, EXTRC Mode244FIGURE 24-9: PIC16F72X maximum Idd vs. Fosc over Vdd, HS Mode, Vcap = 0.1µF245FIGURE 24-10: PIC16LF72X Maximum Idd vs. Fosc over Vdd, HS Mode245FIGURE 24-11: PIC16F72X Typical Idd vs. Fosc over Vdd, HS Mode, Vcap = 0.1µF246FIGURE 24-12: PIC16LF72X Typical Idd vs. Fosc over Vdd, HS Mode246FIGURE 24-13: PIC16F72X Maximum Idd vs. Vdd Over Fosc, XT Mode, Vcap = 0.1µF247FIGURE 24-14: PIC16LF72X Maximum Idd vs. Vdd Over Fosc, XT Mode247FIGURE 24-15: PIC16F72X Typical Idd vs. Vdd Over Fosc, XT Mode, Vcap = 0.1µF248FIGURE 24-16: PIC16LF72X Typical Idd vs. Vdd over Fosc, XT Mode248FIGURE 24-17: PIC16F72X Idd vs. Vdd, LP Mode, Vcap = 0.1µF249FIGURE 24-18: PIC16LF72X Idd vs. Vdd, LP Mode249FIGURE 24-19: PIC16F72X Maximum Idd vs. Fosc over Vdd, INTOSC Mode, Vcap = 0.1µF250FIGURE 24-20: PIC16LF72X Maximum Idd vs. Fosc over Vdd, INTOSC Mode250FIGURE 24-21: PIC16F72X Maximum Idd vs. Fosc over Vdd, INTOSC Mode, Vcap = 0.1µF251FIGURE 24-22: PIC16LF72X Maximum Idd vs. Fosc over Vdd, INTOSC Mode251FIGURE 24-23: PIC16F72X Typical Idd vs. Fosc over Vdd, INTOSC Mode, Vcap = 0.1µF252FIGURE 24-24: PIC16LF72X Typical Idd vs. Fosc over Vdd, INTOSC Mode252FIGURE 24-25: PIC16F72X Typical Idd vs. Fosc over Vdd, INTOSC Mode, Vcap = 0.1µF253FIGURE 24-26: PIC16LF72X Typical Idd vs. Fosc over Vdd, INTOSC Mode253FIGURE 24-27: PIC16F72X Maximum Base Ipd vs. Vdd, Vcap = 0.1µF254FIGURE 24-28: PIC16LF72X Maximum Base Ipd vs. Vdd254FIGURE 24-29: PIC16F72X typical Base Ipd vs. Vdd, Vcap = 0.1µF255FIGURE 24-30: PIC16LF72X Typical Base Ipd vs. Vdd255FIGURE 24-31: PIC16F72X fixed Voltage Reference Ipd vs. Vdd, Vcap = 0.1µF256FIGURE 24-32: PIC16LF72X Fixed Voltage Reference Ipd vs. Vdd256FIGURE 24-33: PIC16F72X BOR Ipd vs. Vdd, Vcap = 0.1µF257FIGURE 24-34: PIC16LF72X BOR Ipd vs. Vdd257FIGURE 24-35: PIC16F72X Cap Sense High Power Ipd vs. Vdd, Vcap = 0.1µF258FIGURE 24-36: PIC16LF72X Cap Sense High Power Ipd vs. Vdd258FIGURE 24-37: PIC16F72X Cap Sense Medium Power Ipd vs. Vdd, Vcap = 0.1µF259FIGURE 24-38: PIC16LF72X cap Sense Medium Power Ipd vs. Vdd259FIGURE 24-39: PIC16F72X Cap Sense low Power Ipd vs. Vdd, Vcap = 0.1µF260FIGURE 24-40: PIC16LF72X Cap Sense Low Power Ipd vs. Vdd260FIGURE 24-41: PIC16F72X T1OSC 32 Khz Ipd vs. Vdd, Vcap = 0.1µF261FIGURE 24-42: PIC16LF72X T1OSC 32 Khz Ipd vs. Vdd261FIGURE 24-43: PIC16F72X TYpical ADC Ipd vs. Vdd, Vcap = 0.1µF262FIGURE 24-44: PIC16LF72X Typical ADC Ipd vs. Vdd262FIGURE 24-45: PIC16F72X ADC Ipd vs. Vdd, Vcap = 0.1µF263FIGURE 24-46: PIC16LF72X ADC Ipd vs. Vdd263FIGURE 24-47: PIC16F72X WDT Ipd vs. Vdd, Vcap = 0.1µF264FIGURE 24-48: PIC16LF72X WDT Ipd vs. Vdd264FIGURE 24-49: TTL Input Threshold Vin vs. Vdd over Temperature265FIGURE 24-50: SCHMITT TRIGGER Input Threshold Vin vs. Vdd Over Temperature265FIGURE 24-51: SCHMITT TRIGGER Input Threshold Vin vs. Vdd Over Temperature266FIGURE 24-52: Voh vs. Ioh Over Temperature, Vdd = 5.5V266FIGURE 24-53: Voh vs. Ioh Over Temperature, Vdd = 3.6V267FIGURE 24-54: Voh vs. Ioh Over Temperature, Vdd = 1.8V267FIGURE 24-55: Vol vs. Iol Over Temperature, Vdd = 5.5V268FIGURE 24-56: Vol vs. Iol Over Temperature, Vdd = 3.6268FIGURE 24-57: Vol vs. Iol over Temperature, Vdd = 1.8V269FIGURE 24-58: PIC16F72X PWRT Period269FIGURE 24-59: PIC16F72X WDT Time-out Period270FIGURE 24-60: PIC16F72X HFINTOSC Wake-up from Sleep Start-up Time270FIGURE 24-61: PIC16F72X A/D Internal RC Oscillator Period271FIGURE 24-62: PIC16F72X Cap Sense Output Current, Power Mode = High271FIGURE 24-63: PIC16F72X Cap Sense Output Current, Power Mode = Medium272FIGURE 24-64: PIC16F72X Cap Sense Output Current, Power Mode = Low272FIGURE 24-65: PIC16F72X Cap sensor Hysteresis, Power Mode = High273FIGURE 24-66: PIC16F72X Cap sensor Hysteresis, power Mode = Medium273FIGURE 24-67: PIC16F72X Cap sensor Hysteresis, power Mode = LOw274FIGURE 24-68: Typical FVR (x1 and x2) vs. Supply Voltage (V) Normalized at 3.0V274FIGURE 24-69: Typical FVR Change vs. Temperature Normalized at 25°C27525.0 Packaging Information27725.1 Package Marking Information277Package Marking Information (Continued)27825.2 Package Details279Appendix A: Data Sheet Revision History291Revision A291Revision B291Revision C291Revision D291Revision E291Appendix B: Migrating From Other PIC® Devices291TABLE B-1: Feature Comparison291INDEX293The Microchip Web Site299Customer Change Notification Service299Customer Support299Reader Response300Product Identification System301Worldwide Sales302크기: 4.44메가바이트페이지: 302Language: English매뉴얼 열기
데이터 시트차례High-Performance RISC CPU:3Flexible Oscillator Structure:3Special Microcontroller Features:3Extreme Low-Power Management PIC16LF1825/1829 with XLP:3Analog Features:3Peripheral Highlights:3Peripheral Highlights (Continued):4Table of Contents9Most Current Data Sheet10Errata10Customer Notification System101.0 Device Overview11TABLE 1-1: Device Peripheral Summary11FIGURE 1-1: PIC16(L)F1825/1829 Block Diagram12TABLE 1-2: PIC16(L)F1825 Pinout Description13TABLE 1-3: PIC16(L)F1829 Pinout Description162.0 Enhanced Mid-range CPU192.1 Automatic Interrupt Context Saving192.2 16-level Stack with Overflow and Underflow192.3 File Select Registers192.4 Instruction Set19FIGURE 2-1: Core Block Diagram203.0 Memory Organization213.1 Program Memory Organization21TABLE 3-1: Device Sizes and Addresses21FIGURE 3-1: Program Memory Map And Stack For PIC16(L)F1825/1829223.1.1 Reading Program Memory as Data22EXAMPLE 3-1: RETLW Instruction22EXAMPLE 3-2: Accessing Program Memory Via FSR233.2 Data Memory Organization233.2.1 Core Registers23Register 3-1: STATUS: STATUS Register243.2.2 Special Function Register253.2.3 General Purpose RAM253.2.4 Common RAM25FIGURE 3-2: Banked Memory Partitioning253.2.5 Device Memory Maps25TABLE 3-2: Memory Map Tables25TABLE 3-3: PIC16(L)F1825/1829 Memory Map, Banks 0-726TABLE 3-4: PIC16(L)F1825/1829 Memory Map, Banks 8-1527TABLE 3-5: PIC16(L)F1825/1829 Memory Map, Banks 16-2328TABLE 3-6: PIC16(L)F1825/1829 Memory Map, Banks 24-3129TABLE 3-7: PIC16(L)F1825/1829 Memory Map, Bank 31303.2.6 Special Function Registers Summary30TABLE 3-8: Special Function Register Summary313.3 PCL and PCLATH42FIGURE 3-3: Loading of PC in Different Situations423.3.1 Modifying PCL423.3.2 Computed goto423.3.3 Computed Function Calls423.3.4 Branching423.4 Stack433.4.1 Accessing the Stack43FIGURE 3-4: Accessing the Stack Example 143FIGURE 3-5: Accessing the Stack Example 244FIGURE 3-6: Accessing the Stack Example 344FIGURE 3-7: Accessing the Stack Example 4453.4.2 Overflow/Underflow Reset453.5 Indirect Addressing45FIGURE 3-8: Indirect Addressing463.5.1 Traditional Data Memory47FIGURE 3-9: Traditional Data Memory Map473.5.2 Linear Data Memory48FIGURE 3-10: Linear Data Memory Map483.5.3 Program Flash Memory48FIGURE 3-11: Program Flash Memory Map484.0 Device Configuration494.1 Configuration Words49Register 4-1: Configuration Word 150Register 4-2: Configuration Word 2524.2 Code Protection534.2.1 Program Memory Protection534.2.2 Data EEPROM Protection534.3 Write Protection534.4 User ID534.5 Device ID and Revision ID54Register 4-3: DEVICEID: Device ID Register(1)545.0 Oscillator Module (With Fail-Safe Clock Monitor)555.1 Overview55FIGURE 5-1: Simplified PIC® MCU Clock Source Block Diagram565.2 Clock Source Types575.2.1 External Clock Sources57FIGURE 5-2: External Clock (EC) Mode Operation57FIGURE 5-3: Quartz Crystal Operation (LP, XT or HS Mode)58FIGURE 5-4: Ceramic Resonator Operation (XT or HS Mode)58FIGURE 5-5: Quartz Crystal Operation (Timer1 Oscillator)59FIGURE 5-6: External RC Modes605.2.2 Internal Clock Sources60FIGURE 5-7: Internal Oscillator Switch Timing645.3 Clock Switching655.3.1 System Clock Select (SCS) BitS655.3.2 Oscillator Start-up Timer Status (OSTS) Bit655.3.3 Timer1 Oscillator655.3.4 Timer1 Oscillator Ready (T1OSCR) Bit655.4 Two-Speed Clock Start-up Mode665.4.1 Two-Speed Start-up Mode Configuration66TABLE 5-1: Oscillator Switching Delays665.4.2 Two-Speed Start-up Sequence675.4.3 Checking Two-Speed Clock Status67FIGURE 5-8: Two-Speed Start-up675.5 Fail-Safe Clock Monitor68FIGURE 5-9: FSCM Block Diagram685.5.1 Fail-Safe Detection685.5.2 Fail-Safe Operation685.5.3 Fail-Safe Condition Clearing685.5.4 Reset or Wake-up from Sleep68FIGURE 5-10: FSCM Timing Diagram695.6 Oscillator Control Registers70Register 5-1: OSCCON: Oscillator Control Register70Register 5-2: OSCSTAT: Oscillator Status Register71Register 5-3: OSCTUNE: Oscillator Tuning Register72TABLE 5-2: Summary of Registers Associated with Clock Sources72TABLE 5-3: Summary of Configuration Word with Clock Sources726.0 Reference Clock Module736.1 Slew Rate736.2 Effects of a Reset736.3 Conflicts with the CLKR Pin736.3.1 Oscillator Modes736.3.2 CLKOUT Function736.4 Operation During Sleep736.5 Reference Clock Control Register74Register 6-1: CLKRCON: Reference Clock Control Register74TABLE 6-1: Summary of Registers Associated with Reference Clock Sources75TABLE 6-2: Summary of Configuration Word with Reference Clock Sources757.0 Resets77FIGURE 7-1: Simplified Block Diagram Of On-Chip Reset Circuit777.1 Power-on Reset (POR)787.1.1 Power-up Timer (PWRT)787.2 Brown-Out Reset (BOR)78TABLE 7-1: BOR Operating Modes787.2.1 BOR is Always On787.2.2 BOR is Off in Sleep787.2.3 BOR Controlled by Software78FIGURE 7-2: Brown-Out Situations79Register 7-1: BORCON: Brown-out Reset Control Register797.3 MCLR80TABLE 7-2: MCLR Configuration807.3.1 MCLR Enabled807.3.2 MCLR Disabled807.4 Watchdog Timer (WDT) Reset807.5 RESET Instruction807.6 Stack Overflow/Underflow Reset807.7 Programming Mode Exit807.8 Power-Up Timer807.9 Start-up Sequence80FIGURE 7-3: Reset Start-up Sequence817.10 Determining the Cause of a Reset82TABLE 7-3: Reset Status Bits and Their Significance82TABLE 7-4: Reset Condition for Special Registers(2)827.11 Power Control (PCON) Register83Register 7-2: PCON: Power Control Register83TABLE 7-5: Summary of Registers Associated with Resets(1)848.0 Interrupts85FIGURE 8-1: Interrupt Logic858.1 Operation868.2 Interrupt Latency86FIGURE 8-2: Interrupt Latency87FIGURE 8-3: INT Pin Interrupt Timing888.3 Interrupts During Sleep898.4 INT Pin898.5 Automatic Context Saving898.6 Interrupt Control Registers908.6.1 INTCON Register90Register 8-1: INTCON: Interrupt Control Register908.6.2 PIE1 Register91Register 8-2: PIE1: Peripheral Interrupt Enable Register 1918.6.3 PIE2 Register92Register 8-3: PIE2: Peripheral Interrupt Enable Register 2928.6.4 PIE3 Register93Register 8-4: PIE3: Peripheral Interrupt Enable Register 3938.6.5 PIE4 Register(1)94Register 8-5: PIE4: Peripheral Interrupt Enable Register 4(1)948.6.6 PIR1 Register95Register 8-6: PIR1: Peripheral Interrupt Request Register 1958.6.7 PIR2 Register96Register 8-7: PIR2: Peripheral Interrupt Request Register 2968.6.8 PIR3 Register97Register 8-8: PIR3: Peripheral Interrupt Request Register 3978.6.9 PIR4 Register(1)98Register 8-9: PIR4: Peripheral Interrupt Request Register 4(1)98TABLE 8-1: Summary of Registers Associated with Interrupts989.0 Power-Down Mode (Sleep)999.1 Wake-up from Sleep999.1.1 Wake-up Using Interrupts99FIGURE 9-1: Wake-up From Sleep Through Interrupt100TABLE 9-1: Summary of Registers Associated with Power-Down Mode10010.0 Watchdog Timer101FIGURE 10-1: Watchdog Timer Block Diagram10110.1 Independent Clock Source10210.2 WDT Operating Modes10210.2.1 WDT Is Always On10210.2.2 WDT Is Off In Sleep10210.2.3 WDT Controlled By Software102TABLE 10-1: WDT Operating Modes10210.3 Time-Out Period10210.4 Clearing the WDT10210.5 Operation During Sleep102TABLE 10-2: WDT Clearing Conditions10210.6 Watchdog Control Register103Register 10-1: WDTCON: Watchdog Timer Control Register103TABLE 10-3: Summary of Registers Associated with Watchdog Timer104TABLE 10-4: Summary of Configuration Word with Watchdog Timer10411.0 Data EEPROM and Flash Program Memory Control10511.1 EEADRL and EEADRH Registers10511.1.1 EECON1 and EECON2 Registers10511.2 Using the Data EEPROM10611.2.1 Reading the Data EEPROM Memory106EXAMPLE 11-1: Data EEPROM Read10611.2.2 Writing to the Data EEPROM Memory10611.2.3 Protection Against Spurious Write10611.2.4 Data EEPROM Operation During Code-Protect106EXAMPLE 11-2: Data EEPROM Write107FIGURE 11-1: Flash Program Memory Read Cycle Execution10711.3 Flash Program Memory Overview108TABLE 11-1: Flash Memory Organization By Device10811.3.1 Reading the Flash Program Memory108EXAMPLE 11-3: Flash Program Memory Read10911.3.2 Erasing Flash Program Memory11011.3.3 Writing to Flash Program Memory110FIGURE 11-2: Block Writes to Flash Program Memory With 32 Write Latches111EXAMPLE 11-4: Erasing One Row of Program Memory112EXAMPLE 11-5: Writing to Flash Program Memory11311.4 Modifying Flash Program Memory11411.5 User ID, Device ID and Configuration Word Access114TABLE 11-2: User ID, Device ID and Configuration Word Access (cfgs = 1)11411.6 Write Verify115EXAMPLE 11-6: EEPROM Write Verify11511.7 EEPROM and Flash Control Registers116Register 11-1: EEDATL: EEPROM Low Byte Data Register116Register 11-2: EEDATH: EEPROM Data High Byte Register116Register 11-3: EEADRL: EEPROM Address Register116Register 11-4: EEADRH: EEPROM Address High Byte Register116Register 11-5: EECON1: EEPROM Control 1 Register117Register 11-6: EECON2: EEPROM Control 2 Register118TABLE 11-3: Summary of Registers Associated with Data EEPROM11812.0 I/O Ports119TABLE 12-1: Port Availability Per Device119FIGURE 12-1: Generic I/O Port Operation119EXAMPLE 12-1: Initializing PORTA11912.1 Alternate Pin Function120Register 12-1: APFCON0: Alternate Pin Function Control Register 0121Register 12-2: APFCON1: Alternate Pin Function Control Register 112212.2 PORTA Registers12312.2.1 ANSELA Register123EXAMPLE 12-2: Initializing PORTA12312.2.2 PORTA Functions and Output Priorities124TABLE 12-2: PORTA Output Priority124Register 12-3: PORTA: PORTA Register125Register 12-4: TRISA: PORTA Tri-State Register125Register 12-5: LATA: PORTA Data Latch Register126Register 12-6: ANSELA: PORTA Analog Select Register126Register 12-7: WPUA: Weak Pull-up PORTA Register127Register 12-8: INLVLA: PORTA Input Level Control Register127TABLE 12-3: Summary of Registers Associated with PORTA128TABLE 12-4: Summary of Configuration Word with PORTA12812.3 PORTB Registers (PIC16(L)F1829 only)12912.3.1 ANSELB Register12912.3.2 PORTB Functions and Output Priorities130TABLE 12-5: PORTB Output Priority130Register 12-9: PORTB: PORTB Register131Register 12-10: TRISB: PORTB Tri-State Register131Register 12-11: LATB: PORTB Data Latch Register131Register 12-12: ANSELB: PORTB Analog Select Register132Register 12-13: WPUB: Weak Pull-up PORTB Register132Register 12-14: INLVLB: PORTB Input Level Control Register132TABLE 12-6: Summary of Registers Associated with PORTB(1)13312.4 PORTC Registers13412.4.1 ANSELC Register13412.4.2 PORTC Functions and Output Priorities135TABLE 12-7: PORTC Output Priority135Register 12-15: PORTC: PORTC Register136Register 12-16: TRISC: PORTC Tri-State Register136Register 12-17: LATC: PORTC Data Latch Register136Register 12-18: ANSELC: PORTC Analog Select Register137Register 12-19: WPUC: Weak Pull-up PORTC Register137Register 12-20: INLVLC: PORTC Input Level Control Register138TABLE 12-8: Summary of Registers Associated with PORTC13813.0 Interrupt-on-Change13913.1 Enabling the Module13913.2 Individual Pin Configuration13913.3 Interrupt Flags13913.4 Clearing Interrupt Flags139EXAMPLE 13-1: Clearing Interrupt Flags (PORTA Example)13913.5 Operation in Sleep139FIGURE 13-1: Interrupt-On-Change Block Diagram (PORTA Example)14013.6 Interrupt-on-Change Registers140Register 13-1: IOCAP: Interrupt-on-Change PORTA Positive Edge Register140Register 13-2: IOCAN: Interrupt-on-Change PORTA Negative Edge Register141Register 13-3: IOCAF: Interrupt-on-Change PORTA Flag Register141Register 13-4: IOCBP: Interrupt-on-Change PORTB Positive Edge Register (PIC16(L)F1829 only)141Register 13-5: IOCBN: Interrupt-on-Change PORTB Negative Edge Register (PIC16(L)F1829 only)142Register 13-6: IOCBF: Interrupt-on-Change PORTB Flag Register (PIC16(L)F1829 only)142TABLE 13-1: Summary of Registers Associated with Interrupt-on-Change14314.0 Fixed Voltage Reference (FVR)14514.1 Independent Gain Amplifiers14514.2 FVR Stabilization Period145FIGURE 14-1: Voltage Reference Block Diagram14514.3 FVR Control Registers146Register 14-1: FVRCON: Fixed Voltage Reference Control Register146TABLE 14-1: Summary of Registers Associated with the Fixed Voltage Reference14615.0 Temperature Indicator Module14715.1 Circuit Operation147EQUATION 15-1: Vout Ranges147FIGURE 15-1: Temperature Circuit Diagram14715.2 Minimum Operating Vdd vs. Minimum Sensing Temperature147TABLE 15-1: Recommended Vdd vs. Range14715.3 Temperature Output14715.4 ADC Acquisition Time14716.0 Analog-to-Digital Converter (ADC) Module149FIGURE 16-1: ADC Block Diagram14916.1 ADC Configuration15016.1.1 Port Configuration15016.1.2 Channel Selection15016.1.3 ADC Voltage Reference15016.1.4 Conversion Clock150TABLE 16-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies151FIGURE 16-2: Analog-to-Digital Conversion Tad Cycles15116.1.5 Interrupts15216.1.6 Result Formatting152FIGURE 16-3: 10-Bit A/D Conversion Result Format15216.2 ADC Operation15316.2.1 Starting a Conversion15316.2.2 Completion of a Conversion15316.2.3 Terminating a Conversion15316.2.4 ADC Operation During Sleep15316.2.5 Special Event Trigger153TABLE 16-2: Special Event Trigger15316.2.6 A/D Conversion Procedure154EXAMPLE 16-1: A/D Conversion15416.2.7 ADC Register Definitions155Register 16-1: ADCON0: A/D Control Register 0155Register 16-2: ADCON1: A/D Control Register 1156Register 16-3: ADRESH: ADC Result Register High (ADRESH) ADFM = 0157Register 16-4: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0157Register 16-5: ADRESH: ADC Result Register High (ADRESH) ADFM = 1158Register 16-6: ADRESL: ADC Result Register Low (ADRESL) ADFM = 115816.3 A/D Acquisition Requirements159EQUATION 16-1: Acquisition Time Example159FIGURE 16-4: Analog Input Model160FIGURE 16-5: ADC Transfer Function160TABLE 16-3: Summary of Registers Associated with ADC16117.0 Digital-to-Analog Converter (DAC) Module16317.1 Output Voltage Selection163EQUATION 17-1: DAC Output Voltage16317.2 Ratiometric Output Level16317.3 DAC Voltage Reference Output163FIGURE 17-1: Digital-to-Analog Converter Block Diagram164FIGURE 17-2: Voltage Reference Output Buffer Example16417.4 Low-Power Voltage State16517.4.1 Output Clamped to Positive Voltage Source16517.4.2 Output Clamped to Negative Voltage Source165FIGURE 17-3: Output Voltage Clamping Examples16517.5 Operation During Sleep16517.6 Effects of a Reset16517.7 DAC Control Registers166Register 17-1: DACCON0: Voltage Reference Control Register 0166Register 17-2: DACCON1: Voltage Reference Control Register 1166TABLE 17-1: Summary of Registers Associated with the DAC Module16718.0 SR Latch16918.1 Latch Operation16918.2 Latch Output16918.3 Effects of a Reset169FIGURE 18-1: SR Latch Simplified Block Diagram170TABLE 18-1: SRCLK Frequency Table171Register 18-1: SRCON0: SR Latch Control 0 Register171Register 18-2: SRCON1: SR Latch Control 1 Register172TABLE 18-2: Summary of Registers Associated with SR Latch Module17319.0 Comparator Module17519.1 Comparator Overview175FIGURE 19-1: Single Comparator175FIGURE 19-2: Comparator Module Simplified Block Diagram17519.2 Comparator Control17619.2.1 Comparator Enable17619.2.2 Comparator Output Selection17619.2.3 Comparator Output Polarity176TABLE 19-1: Comparator Output State vs. Input Conditions17619.2.4 Comparator Speed/Power Selection17619.3 Comparator Hysteresis17619.4 Timer1 Gate Operation17719.4.1 Comparator Output Synchronization17719.5 Comparator Interrupt17719.6 Comparator Positive Input Selection17719.7 Comparator Negative Input Selection17719.8 Comparator Response Time17719.9 Interaction with ECCP Logic17819.10 Analog Input Connection Considerations178FIGURE 19-3: Analog Input Model178Register 19-1: CMxCON0: Comparator cx Control Register 0179Register 19-2: CMxCON1: Comparator Cx Control Register 1180Register 19-3: CMOUT: Comparator Output Register180TABLE 19-2: Summary of Registers Associated with Comparator Module18120.0 Timer0 Module18320.1 Timer0 Operation18320.1.1 8-bit Timer Mode18320.1.2 8-Bit Counter Mode183FIGURE 20-1: Block Diagram of the Timer018320.1.3 Software Programmable Prescaler18420.1.4 Timer0 Interrupt18420.1.5 8-Bit Counter Mode Synchronization18420.1.6 Operation During Sleep18420.2 Option and Timer0 Control Register185Register 20-1: OPTION_REG: Option Register185TABLE 20-1: Summary of Registers Associated with Timer018521.0 Timer1 Module with Gate Control187FIGURE 21-1: Timer1 Block Diagram18721.1 Timer1 Operation188TABLE 21-1: Timer1 Enable Selections18821.2 Clock Source Selection18821.2.1 Internal Clock Source18821.2.2 External Clock Source188TABLE 21-2: Clock Source Selections18821.3 Timer1 Prescaler18921.4 Timer1 Oscillator18921.5 Timer1 Operation in Asynchronous Counter Mode18921.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode18921.6 Timer1 Gate18921.6.1 Timer1 Gate Enable189TABLE 21-3: Timer1 Gate Enable Selections18921.6.2 Timer1 Gate Source Selection190TABLE 21-4: Timer1 Gate Sources19021.6.3 Timer1 Gate Toggle Mode19021.6.4 Timer1 Gate Single-Pulse Mode19021.6.5 Timer1 Gate Value Status19021.6.6 Timer1 Gate Event Interrupt19021.7 Timer1 Interrupt19121.8 Timer1 Operation During Sleep19121.9 ECCP/CCP Capture/Compare Time Base19121.10 ECCP/CCP Special Event Trigger191FIGURE 21-2: Timer1 Incrementing Edge191FIGURE 21-3: Timer1 Gate Enable Mode192FIGURE 21-4: Timer1 Gate Toggle Mode192FIGURE 21-5: Timer1 Gate Single-Pulse Mode193FIGURE 21-6: Timer1 Gate Single-Pulse and Toggle Combined Mode19421.11 Timer1 Control Register195Register 21-1: T1CON: Timer1 Control Register19521.12 Timer1 Gate Control Register196Register 21-2: T1GCON: Timer1 Gate Control Register196TABLE 21-5: Summary of Registers Associated with Timer119722.0 Timer2/4/6 Modules199FIGURE 22-1: Timer2/4/6 Block Diagram19922.1 Timer2/4/6 Operation20022.2 Timer2/4/6 Interrupt20022.3 Timer2/4/6 Output20022.4 Timer2/4/6 Operation During Sleep20022.5 Timer2 Control Register201Register 22-1: TxCON: Timer2/Timer4/Timer6 Control Register201TABLE 22-1: Summary of Registers Associated With Timer2/4/620223.0 Data Signal Modulator203FIGURE 23-1: Simplified Block Diagram of the Data Signal Modulator20323.1 DSM Operation20423.2 Modulator Signal Sources20423.3 Carrier Signal Sources20423.4 Carrier Synchronization204FIGURE 23-2: ON OFF Keying (OOK) Synchronization205EXAMPLE 23-1: No Synchronization (MDSHSYNC = 0, MDCLSYNC = 0)205FIGURE 23-3: Carrier High Synchronization (MDSHSYNC = 1, MDCLSYNC = 0)205FIGURE 23-4: Carrier Low Synchronization (MDSHSYNC = 0, MDCLSYNC = 1)206FIGURE 23-5: Full Synchronization (MDSHSYNC = 1, MDCLSYNC = 1)20623.5 Carrier Source Polarity Select20723.6 Carrier Source Pin Disable20723.7 Programmable Modulator Data20723.8 Modulator Source Pin Disable20723.9 Modulated Output Polarity20723.10 Slew Rate Control20723.11 Operation in Sleep Mode20723.12 Effects of a Reset207Register 23-1: MDCON: Modulation Control Register208Register 23-2: MDSRC: Modulation Source Control Register209Register 23-3: MDCARH: Modulation High Carrier Control Register210Register 23-4: MDCARL: Modulation Low Carrier Control Register211TABLE 23-1: Summary of Registers Associated with Data Signal Modulator Mode21124.0 Capture/Compare/PWM Modules213TABLE 24-1: PWM Resources21324.1 Capture Mode21424.1.1 CCP pin Configuration214FIGURE 24-1: Capture Mode Operation Block Diagram21424.1.2 Timer1 Mode Resource21424.1.3 Software Interrupt Mode21424.1.4 CCP Prescaler214EXAMPLE 24-1: Changing Between Capture Prescalers21424.1.5 Capture During Sleep21524.1.6 Alternate Pin Locations215TABLE 24-2: Summary of Registers Associated with Capture21524.2 Compare Mode216FIGURE 24-2: Compare Mode Operation Block Diagram21624.2.1 CCP Pin Configuration21624.2.2 Timer1 Mode Resource21624.2.3 Software Interrupt Mode21624.2.4 Special Event Trigger216TABLE 24-3: Special Event Trigger21624.2.5 Compare During Sleep21724.2.6 Alternate Pin Locations217TABLE 24-4: Summary of Registers Associated with Compare21724.3 PWM Overview21824.3.1 Standard PWM Operation218FIGURE 24-3: CCP PWM Output Signal218FIGURE 24-4: Simplified PWM Block Diagram21824.3.2 Setup for PWM Operation21924.3.3 Timer2/4/6 Timer Resource21924.3.4 PWM Period219EQUATION 24-1: PWM Period21924.3.5 PWM Duty Cycle219EQUATION 24-2: Pulse Width219EQUATION 24-3: Duty Cycle Ratio21924.3.6 PWM Resolution220EQUATION 24-4: PWM Resolution220TABLE 24-5: Example PWM Frequencies and Resolutions (Fosc = 32 MHz)220TABLE 24-6: Example PWM Frequencies and Resolutions (Fosc = 20 MHz)220TABLE 24-7: Example PWM Frequencies and Resolutions (Fosc = 8 MHz)22024.3.7 Operation in Sleep Mode22124.3.8 Changes in System Clock Frequency22124.3.9 Effects of Reset22124.3.10 Alternate Pin Locations221TABLE 24-8: Summary of Registers Associated with Standard PWM22124.4 PWM (Enhanced Mode)222FIGURE 24-5: Example Simplified Block Diagram of the Enhanced PWM Mode222TABLE 24-9: Example Pin Assignments for Various PWM Enhanced Modes223FIGURE 24-6: Example PWM (Enhanced Mode) Output Relationships (Active-High State)223FIGURE 24-7: Example Enhanced PWM Output Relationships (Active-Low State)22424.4.1 Half-Bridge Mode225FIGURE 24-8: Example of Half- Bridge PWM Output225FIGURE 24-9: Example of Half-Bridge Applications22524.4.2 Full-Bridge Mode226FIGURE 24-10: Example of Full-Bridge Application226FIGURE 24-11: Example of Full-Bridge PWM Output227FIGURE 24-12: Example of PWM Direction Change228FIGURE 24-13: Example of PWM Direction Change at Near 100% Duty Cycle22924.4.3 Enhanced PWM Auto- shutdown mode230FIGURE 24-14: PWM Auto-shutdown With Firmware Restart (PxRSEN = 0)23024.4.4 Auto-restart Mode231FIGURE 24-15: PWM Auto-shutdown With Auto-restart (PxRSEN = 1)23124.4.5 Programmable Dead-Band Delay Mode232FIGURE 24-16: Example of Half- Bridge PWM Output232FIGURE 24-17: Example of Half-Bridge Applications23224.4.6 PWM Steering Mode233FIGURE 24-18: Simplified Steering Block Diagram23324.4.7 Start-up Considerations23424.4.8 Alternate Pin Locations234FIGURE 24-19: Example of Steering Event at End of Instruction (STRxSYNC = 0)234FIGURE 24-20: Example of Steering Event at Beginning of Instruction (STRxSYNC = 1)234TABLE 24-10: Summary of Registers Associated with Enhanced PWM23524.5 CCP Control Registers236Register 24-1: CCPXCON: CCPx Control Register236Register 24-2: CCPTMRS: PWM Timer Selection Control Register 0237Register 24-3: CCPxAS: CCPx Auto-shutdown Control Register238Register 24-4: PWMxCON: Enhanced PWM Control Register239Register 24-5: PSTRxCON: PWM Steering Control Register(1)24025.0 Master Synchronous Serial Port (MSSP1 and MSSP2) Module24125.1 Master SSPx (MSSPx) Module Overview241FIGURE 25-1: MSSPx Block Diagram (SPI mode)241FIGURE 25-2: MSSPx Block Diagram (I2C™ Master mode)242FIGURE 25-3: MSSPx Block Diagram (I2C™ Slave mode)24325.2 SPI Mode Overview244FIGURE 25-4: SPI Master and Multiple Slave Connection24525.2.1 SPI Mode Registers24525.2.2 SPI Mode Operation245FIGURE 25-5: SPI Master/Slave Connection24625.2.3 SPI Master Mode247FIGURE 25-6: SPI Mode Waveform (Master Mode)24725.2.4 SPI Slave Mode24825.2.5 Slave Select Synchronization248FIGURE 25-7: SPI Daisy-Chain Connection249FIGURE 25-8: Slave Select Synchronous Waveform249FIGURE 25-9: SPI Mode Waveform (Slave Mode With CKE = 0)250FIGURE 25-10: SPI Mode Waveform (SLAve Mode With CKE = 1)25025.2.6 SPI Operation in Sleep Mode251TABLE 25-1: Summary of Registers Associated with SPI Operation25125.3 I2C Mode Overview252FIGURE 25-11: I2C Master/ Slave Connection25225.3.1 Clock Stretching25325.3.2 Arbitration25325.4 I2C Mode Operation25425.4.1 Byte Format25425.4.2 Definition of I2C Terminology25425.4.3 SDAx and SCLx Pins25425.4.4 SDAX Hold Time254TABLE 25-2: I2C Bus Terms25425.4.5 Start Condition25425.4.6 Stop Condition25525.4.7 Restart Condition25525.4.8 Start/Stop Condition Interrupt Masking255FIGURE 25-12: I2C START and STOP Conditions255FIGURE 25-13: I2C Restart Condition25525.4.9 Acknowledge Sequence25625.5 I2C Slave Mode Operation25625.5.1 Slave Mode Addresses256FIGURE 25-14: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0)258FIGURE 25-15: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)259FIGURE 25-16: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1)260FIGURE 25-17: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1)26125.5.2 SLAVE Transmission262FIGURE 25-18: I2C Slave, 7-Bit Address, Transmission (AHEN = 0)263FIGURE 25-19: I2C Slave, 7-Bit Address, Transmission (AHEN = 1)26525.5.3 Slave mode 10-bit Address Reception26625.5.4 10-bit Addressing With Address Or Data Hold266FIGURE 25-20: I2C Slave, 10-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)267FIGURE 25-21: I2C Slave, 10-Bit Address, Reception (SeN = 0, AHEN = 1, DHEN = 0)268FIGURE 25-22: I2C Slave, 10-Bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0)26925.5.5 Clock Stretching27025.5.6 Clock Synchronization and the CKP bit270FIGURE 25-23: Clock Synchronization Timing27025.5.7 General Call Address Support271FIGURE 25-24: Slave Mode General Call Address Sequence27125.5.8 SSPx Mask Register27125.6 I2C Master Mode27225.6.1 I2C Master Mode Operation27225.6.2 Clock Arbitration273FIGURE 25-25: Baud Rate Generator Timing with Clock Arbitration27325.6.3 WCOL Status Flag27325.6.4 I2C Master Mode Start Condition Timing274FIGURE 25-26: First Start Bit Timing27425.6.5 I2C Master Mode Repeated Start Condition Timing275FIGURE 25-27: Repeat Start Condition Waveform27525.6.6 I2C Master Mode Transmission276FIGURE 25-28: I2C Master Mode Waveform (Transmission, 7 or 10-Bit Address)27725.6.7 I2C Master Mode Reception278FIGURE 25-29: I2C Master Mode Waveform (Reception, 7-Bit Address)27925.6.8 Acknowledge Sequence Timing28025.6.9 Stop Condition Timing280FIGURE 25-30: Acknowledge Sequence Waveform280FIGURE 25-31: Stop Condition Receive or Transmit Mode28025.6.10 Sleep Operation28125.6.11 Effects of a Reset28125.6.12 Multi-Master Mode28125.6.13 Multi -Master Communication, Bus Collision and Bus Arbitration281FIGURE 25-32: Bus Collision Timing for Transmit and Acknowledge281FIGURE 25-33: Bus Collision During Start Condition (SDAx Only)282FIGURE 25-34: Bus Collision During Start Condition (SCLx = 0)283FIGURE 25-35: BRG Reset Due to SDA Arbitration During Start Condition283FIGURE 25-36: Bus Collision During a Repeated Start Condition (Case 1)284FIGURE 25-37: Bus Collision During Repeated Start Condition (Case 2)284FIGURE 25-38: Bus Collision During a Stop Condition (Case 1)285FIGURE 25-39: Bus Collision During a Stop Condition (Case 2)285TABLE 25-3: Summary of Registers Associated with I2C™ Operation28625.7 Baud Rate Generator287FIGURE 25-40: Baud Rate Generator Block Diagram287TABLE 25-4: MSSPx Clock Rate w/BRG287Register 25-1: SSPxSTAT: SSPx STATUS Register288Register 25-2: SSPxCON1: SSPx Control Register 1289Register 25-3: SSPxCON2: SSPx Control Register 2290Register 25-4: SSPxCON3: SSPx Control Register 3291Register 25-5: SSPMSK: SSPx Mask Register292Register 25-6: SSPxADD: MSSPx Address and Baud Rate Register (I2C Mode)29226.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)293FIGURE 26-1: EUSART Transmit Block Diagram293FIGURE 26-2: EUSART Receive Block Diagram29426.1 EUSART Asynchronous Mode29526.1.1 EUSART Asynchronous Transmitter295FIGURE 26-3: Asynchronous Transmission296FIGURE 26-4: Asynchronous Transmission (Back-to-Back)297TABLE 26-1: Summary of Registers Associated with Asynchronous Transmission29726.1.2 EUSART Asynchronous Receiver298FIGURE 26-5: Asynchronous Reception300TABLE 26-2: Summary of Registers Associated with Asynchronous Reception30126.2 Clock Accuracy with Asynchronous Operation302Register 26-1: TXSTA: Transmit Status and Control Register302Register 26-2: RCSTA: Receive Status and Control Register (1)303Register 26-3: BAUDCON: Baud Rate Control Register30426.3 EUSART Baud Rate Generator (BRG)305EXAMPLE 26-1: Calculating Baud Rate Error305TABLE 26-3: Baud Rate Formulas306TABLE 26-4: Summary of Registers Associated with the Baud Rate Generator306TABLE 26-5: BAUD Rates for Asynchronous Modes30726.3.1 Auto-Baud Detect310TABLE 26-6: BRG Counter Clock Rates310FIGURE 26-6: Automatic Baud Rate Calibration31026.3.2 Auto-baud Overflow31126.3.3 Auto-Wake-up on Break311FIGURE 26-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation312FIGURE 26-8: Auto-Wake-up Bit (WUE) Timings During Sleep31226.3.4 BREAK Character Sequence31326.3.5 Receiving a Break Character313FIGURE 26-9: Send Break Character Sequence31326.4 EUSART Synchronous Mode31426.4.1 Synchronous Master Mode314FIGURE 26-10: Synchronous Transmission315FIGURE 26-11: Synchronous Transmission (Through TXEN)315TABLE 26-7: Summary of Registers Associated with Synchronous Master Transmission315FIGURE 26-12: Synchronous Reception (Master Mode, SREN)317TABLE 26-8: Summary of Registers Associated with Synchronous Master Reception31726.4.2 Synchronous Slave Mode318TABLE 26-9: Summary of Registers Associated with Synchronous Slave Transmission318TABLE 26-10: Summary of Registers Associated with Synchronous Slave Reception31926.5 EUSART Operation During Sleep32026.5.1 Synchronous Receive During Sleep32026.5.2 Synchronous Transmit During Sleep32026.5.3 Alternate Pin Locations32027.0 Capacitive Sensing (CPS) Module321FIGURE 27-1: Capacitive Sensing Block Diagram321FIGURE 27-2: Capacitive Sensing Oscillator Block Diagram32227.1 Analog MUX32327.2 Capacitive Sensing Oscillator32327.3 Voltage References32327.4 Power Modes324TABLE 27-1: Power Mode Selection32427.5 Timer Resources32527.6 Fixed Time Base32527.6.1 Timer032527.6.2 Timer1325TABLE 27-2: Timer1 Enable Function32527.7 Software Control32527.7.1 Nominal Frequency (No Capacitive Load)32527.7.2 Reduced Frequency (Additional Capacitive Load)32527.7.3 Frequency Threshold32627.8 Operation during Sleep326Register 27-1: CPSCON0: Capacitive Sensing Control Register 0327Register 27-2: CPSCON1: Capacitive Sensing Control Register 1328TABLE 27-3: Summary of Registers Associated with Capacitive Sensing32828.0 In-Circuit Serial Programming™ (ICSP™)32928.1 High-Voltage Programming Entry Mode329FIGURE 28-1: Vpp Limiter Example Circuit32928.2 Low-Voltage Programming Entry Mode33028.3 Common Programming Interfaces330FIGURE 28-2: ICD RJ-11 Style Connector Interface330FIGURE 28-3: PICkit™ Style Connector Interface330FIGURE 28-4: Typical Connection for ICSP™ Programming33129.0 Instruction Set Summary33329.1 Read-Modify-Write Operations333TABLE 29-1: Opcode Field Descriptions333TABLE 29-2: Abbreviation Descriptions333FIGURE 29-1: General Format for Instructions334TABLE 29-3: PIC16(L)F1825/1829 Enhanced Instruction Set335TABLE 29-3: PIC16(L)F1825/1829 Enhanced Instruction Set (Continued)33629.2 Instruction Descriptions33730.0 Electrical Specifications347Absolute Maximum Ratings(†)347FIGURE 30-1: PIC16F1825/1829 Voltage Frequency Graph, -40°C £ Ta £ +125°C348FIGURE 30-2: PIC16LF1825/1829 Voltage Frequency Graph, -40°C £ Ta £ +125°C348FIGURE 30-3: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature34930.1 DC Characteristics: PIC16(L)F1825/1829-I/E (Industrial, Extended)350FIGURE 30-4: POR and POR Rearm with Slow Rising Vdd35130.2 DC Characteristics: PIC16(L)F1825/1829-I/E (Industrial, Extended)35230.3 DC Characteristics: PIC16(L)F1825/1829-I/E (Power-Down)35530.4 DC Characteristics: PIC16(L)F1825/1829-I/E35730.5 Memory Programming Requirements35830.6 Thermal Considerations35930.7 Timing Parameter Symbology360FIGURE 30-5: Load Conditions36030.8 AC Characteristics: PIC16(L)F1825/1829-I/E361FIGURE 30-6: Clock Timing361TABLE 30-1: Clock Oscillator Timing Requirements361TABLE 30-2: Oscillator Parameters362TABLE 30-3: PLL Clock Timing Specifications (Vdd = 2.7V to 5.5V)362FIGURE 30-7: CLKOUT and I/O Timing362TABLE 30-4: CLKOUT and I/O Timing Parameters363FIGURE 30-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing363FIGURE 30-9: Brown-Out Reset Timing and Characteristics364TABLE 30-5: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-Out Reset Parameters365FIGURE 30-10: Timer0 and Timer1 External Clock Timings365TABLE 30-6: Timer0 and Timer1 External Clock Requirements366FIGURE 30-11: Capture/Compare/PWM Timings (CCP)366TABLE 30-7: Capture/Compare/PWM Requirements (CCP)366TABLE 30-8: PIC16(L)F1825/1829 A/D Converter (ADC) Characteristics(1,2,3)367TABLE 30-9: PIC16(L)F1825/1829 A/D Conversion Requirements367FIGURE 30-12: PIC16(L)F1825/1829 A/D Conversion Timing (Normal Mode)368FIGURE 30-13: PIC16(L)F1825/1829 A/D Conversion Timing (Sleep Mode)368TABLE 30-10: Comparator Specifications369TABLE 30-11: Digital-to-Analog Converter (DAC) Specifications369TABLE 30-12: PIC16(L)F1825/1829 Low Dropout (LDO) Regulator Characteristics:369FIGURE 30-14: USART Synchronous Transmission (Master/Slave) Timing370TABLE 30-13: USART Synchronous Transmission Requirements370FIGURE 30-15: USART Synchronous Receive (Master/Slave) Timing370TABLE 30-14: USART Synchronous Receive Requirements370FIGURE 30-16: SPI Master Mode Timing (CKE = 0, SMP = 0)371FIGURE 30-17: SPI Master Mode Timing (CKE = 1, SMP = 1)371FIGURE 30-18: SPI Slave Mode Timing (CKE = 0)372FIGURE 30-19: SPI Slave Mode Timing (CKE = 1)372TABLE 30-15: SPI Mode Requirements373FIGURE 30-20: I2C™ Bus Start/Stop Bits Timing374TABLE 30-16: I2C™ Bus Start/Stop Bits Requirements374FIGURE 30-21: I2C™ Bus Data Timing374TABLE 30-17: I2C™ Bus Data Requirements375TABLE 30-18: Cap Sense Oscillator Specifications376FIGURE 30-22: Cap Sense Oscillator37631.0 DC and AC Characteristics Graphs and Charts377FIGURE 31-1: Idd, LP Oscillator Mode (Fosc = 32 kHz), PIC16LF1825/1829 only378FIGURE 31-2: Idd, LP Oscillator Mode (Fosc = 32 kHz), PIC16F1825/1829 only378FIGURE 31-3: Idd Typical, XT and EXTRC Oscillator, PIC16LF1825/1829 only379FIGURE 31-4: Idd Maximum, XT and EXTRC Oscillator, PIC16LF1825/1829 only379FIGURE 31-5: Idd Typical, XT and EXTRC Oscillator, PIC16F1825/1829 only380FIGURE 31-6: Idd Maximum, XT and EXTRC Oscillator, PIC16F1825/1829 only380FIGURE 31-7: Idd Typical, EC Oscillator, Medium-Power Mode, PIC16LF1825/1829 only381FIGURE 31-8: Idd Maximum, EC Oscillator, Medium-Power Mode, PIC16LF1825/1829 only381FIGURE 31-9: Idd Typical, EC Oscillator, Medium-Power Mode, PIC16F1825/1829 only382FIGURE 31-10: Idd Maximum, EC Oscillator, Medium-Power Mode, PIC16F1825/1829 only382FIGURE 31-11: Idd, LFINTOSC Mode (Fosc = 31 kHz), PIC16LF1825/1829 only383FIGURE 31-12: Idd, LFINTOSC Mode (Fosc = 31 kHz), PIC16F1825/1829 only383FIGURE 31-13: Idd, MFINTOSC Mode (Fosc = 500 kHz), PIC16LF1825/1829 only384FIGURE 31-14: Idd, MFINTOSC Mode (Fosc = 500 kHz), PIC16F1825/1829 only384FIGURE 31-15: Idd Typical, HFINTOSC Mode, PIC16LF1825/1829 only385FIGURE 31-16: Idd Maximum, HFINTOSC Mode, PIC16LF1825/1829 only385FIGURE 31-17: Idd Typical, HFINTOSC Mode, PIC16F1825/1829 only386FIGURE 31-18: Idd Maximum, HFINTOSC Mode, PIC16F1825/1829 only386FIGURE 31-19: Idd, HS Oscillator, 32 MHz (8 MHz + 4xPLL), PIC16LF1825/1829 only387FIGURE 31-20: Idd, HS Oscillator, 32 MHz (8 MHz + 4xPLL), PIC16F1825/1829 only387FIGURE 31-21: Ipd Base, Low-Power Sleep Mode, PIC16LF1825/1829 Only388FIGURE 31-22: Ipd Base, Low-Power Sleep Mode, PIC16F1825/1829 only388FIGURE 31-23: Ipd, Watchdog Timer (WDT), PIC16LF1825/1829 only389FIGURE 31-24: Ipd, Watchdog Timer (WDT), PIC16F1825/1829 only389FIGURE 31-25: Ipd, Fixed Voltage Reference (FVR), PIC16LF1825/1829 only390FIGURE 31-26: Ipd, Fixed Voltage Reference (FVR), PIC16F1825/1829 only390FIGURE 31-27: Ipd, Brown-Out Reset (BOR), PIC16LF1825/1829 only391FIGURE 31-28: Ipd, Brown-Out Reset (BOR), PIC16F1825/1829 only391FIGURE 31-29: Ipd, Timer1 Oscillator (Fosc = 32 kHz), PIC16LF1825/1829 only392FIGURE 31-30: Ipd, Timer1 Oscillator (Fosc = 32 kHz), PIC16F1825/1829 only392FIGURE 31-31: Ipd, Capacitive Sensing (CPS) Module, Low-Current Range, CPSRM = 0, PIC16LF1825/1829 only393FIGURE 31-32: Ipd, Capacitive Sensing (CPS) Module, Low-Current Range, CPSRM = 0, PIC16F1825/1829 only393FIGURE 31-33: Ipd, Capacitive Sensing (CPS) Module, Medium-Current Range, CPSRM = 0, PIC16LF1825/1829 only394FIGURE 31-34: Ipd, Capacitive Sensing (CPS) Module, Medium-Current Range, CPSRM = 0, PIC16F1825/1829 only394FIGURE 31-35: Ipd, Capacitive Sensing (CPS) Module, High-Current Range, CPSRM = 0, PIC16LF1825/1829 only395FIGURE 31-36: Ipd, Capacitive Sensing (CPS) Module, High-Current Range, CPSRM = 0, PIC16F1825/1829 only395FIGURE 31-37: Ipd, Comparator, Low-Power Mode (CxSP = 0), PIC16LF1825/1829 only396FIGURE 31-38: Ipd, Comparator, Low-Power Mode (CxSP = 0), PIC16F1825/1829 only396FIGURE 31-39: Ipd, Comparator, Normal-Power Mode (CxSP = 1), PIC16LF1825/1829 only397FIGURE 31-40: Ipd, Comparator, Normal-Power Mode (CxSP = 1), PIC16F1825/1829 only397FIGURE 31-41: Voh vs. Ioh Over Temperature (Vdd = 5.0V), PIC16F1825/1829 only398FIGURE 31-42: Vol vs. Iol Over Temperature (Vdd = 5.0V), PIC16F1825/1829 only398FIGURE 31-43: Voh vs. Ioh Over Temperature (Vdd = 3.0V)399FIGURE 31-44: Vol vs. Iol Over Temperature (Vdd = 3.0V)399FIGURE 31-45: Voh vs. Ioh Over Temperature (Vdd = 1.8V)400FIGURE 31-46: Vol vs. Iol Over Temperature (Vdd = 1.8V)400FIGURE 31-47: POR Release Voltage401FIGURE 31-48: POR Rearm Voltage, PIC16F1825/1829 Only401FIGURE 31-49: Brown-out Reset Voltage, BORV = 1402FIGURE 31-50: Brown-out Reset Hysteresis, BORV = 1402FIGURE 31-51: Brown-out Reset Voltage, BORV = 0403FIGURE 31-52: Brown-out Reset Hysteresis, BORV = 0403FIGURE 31-53: WDT Time-out Period404FIGURE 31-54: PWRT Period404FIGURE 31-55: Comparator Hysteresis, Normal-Power Mode (CxSP = 1, CxHYS = 1)405FIGURE 31-56: Comparator Hysteresis, Low-Power Mode (CxSP = 0, CxHYS = 1)405FIGURE 31-57: Comparator Response Time, Normal-Power Mode (CxSP = 1)406FIGURE 31-58: Comparator Response Time Over Temperature, Normal-Power Mode (CxSP = 1)406FIGURE 31-59: Comparator Input Offset at 25°C, Normal-Power Mode (CxSP = 1), PIC16F1825/1829 Only40732.0 Development Support40932.1 MPLAB Integrated Development Environment Software40932.2 MPLAB C Compilers for Various Device Families41032.3 HI-TECH C for Various Device Families41032.4 MPASM Assembler41032.5 MPLINK Object Linker/ MPLIB Object Librarian41032.6 MPLAB Assembler, Linker and Librarian for Various Device Families41032.7 MPLAB SIM Software Simulator41132.8 MPLAB REAL ICE In-Circuit Emulator System41132.9 MPLAB ICD 3 In-Circuit Debugger System41132.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express41132.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express41232.12 MPLAB PM3 Device Programmer41232.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits41233.0 Packaging Information41333.1 Package Marking Information41333.1 Package Marking Information41433.1 Package Marking Information41533.1 Package Marking Information41633.2 Package Details417Appendix A: Data Sheet Revision History435Appendix B: Migrating From Other PIC® Devices435TABLE B-1: Feature Comparison435INDEX437A437B437C437D438E438F439I439L439M440O440P440R440S441T442U443V443W443The Microchip Web Site445Customer Change Notification Service445Customer Support445Reader Response446Product Identification System447Worldwide Sales448크기: 7.69메가바이트페이지: 448Language: English매뉴얼 열기
