사용자 설명서차례1 About This Manual12 Introduction22.1 Product Description22.2 Unpacking Instructions3Figure 1. HW400c/2 Block Diagram32.3 Handling Procedures42.4 Hardware Installation of the HW400c/242.5 Returns/Service52.6 Operating Environment5Table 1. HW400c/2 Operating Environment52.7 Mean Time Between Failures (MTBF)62.8 Regulatory Agency Certifications72.8.1 Safety72.8.2 US and Canadian Emissions72.8.3 European Emissions and Immunity72.9 Agency Compliance72.10 Physical Properties8Figure 2. The HW400c/2 PTMC Processing Platform8Table 2. HW400c/2 Physical Dimensions82.10.1 HW400c/2 Front Panel9Figure 3. HW400c/2 Front Panel92.10.2 Part number and serial number102.10.3 Bus Keying102.10.3.1 Compact PCI102.10.3.2 PTMC Site102.10.4 Power Requirements11Table 3. HW400c/2 power requirements VIO = 5.0V11Table 4. HW400c/2 power requirements VIO = 3.3V112.10.5 Switches122.10.6 Product Configurations12Table 5. HW400c/2 Order time options123 Functional Blocks133.1 PowerPC Processor133.1.1 MPC744X Development/Debug Support13Table 6. HW400c/2 Processor Options133.1.2 Console port143.1.3 Pushbutton Reset / Interrupt14Figure 4. Console port pin out14Figure 5. J8, J9 Reset/NMI header14Figure 6. J8 and J9 with optional Reset/NMI cable15Table 7. J8 and J9 pin out153.1.4 COP/JTAG Port163.1.5 Special Purpose Jumper Block16Figure 7. Optional Reset/NMI switch16Figure 8. COP/JTAG Pinout16Figure 9. J7 Special purpose jumper block163.1.5.1 Jumper Pins173.2 MV64462 System Controller173.2.1 System Bus173.2.2 Dual Data Rate (DDR) SDRAM17Table 8. J7 pin functions173.2.3 Host PCI Bus183.2.3.1 Operation Without CompactPCI Bus183.2.4 Local PCI Bus183.2.5 Serial EEPROM19Table 9. Microwire EEPROM Contents, Factory Area20Table 10. Microwire EEPROM Contents, Uboot Area213.2.6 MV64462 Ethernet Interface223.2.7 MV64462 Device Interface223.2.7.1 SRAM Device223.2.7.2 Boot PROM223.2.7.3 Disk-on-Chip223.2.7.4 CT Bus Controller233.2.7.5 CPLD233.2.8 Watchdog Timer233.2.9 Reset233.2.10 Multi-Purpose Port (MPP) Usage24Table 11. MV64462 Multi-Purpose Port Assignments243.3 Computer Telephony Bus Controller253.3.1 H.110 Interface (T8110L)253.3.2 T8110L Clocking Interface (T8110L)25Table 12. LSC Assignments25Figure 10. Local CT Bus Clocking Block Diagram26Figure 11. Local CT Bus Clock Generation263.3.3 Operation in Non-H.110 Backplane273.4 Layer 2 Ethernet Switch27Table 13. LREF [3:2] Assignments27Table 14. Layer 2 Switch Port Assignments273.4.1 Switch Registers Initialization and Monitoring283.4.2 MV64462 System Controller Ethernet Interface283.4.3 Front Panel (RJ-45) Ethernet Interface28Figure 12. Front panel Ethernet RJ-45 LEDs283.4.4 PT5MC Ethernet Ports293.4.5 CompactPCI Packet Switch Backplane (cPSB) Ports293.4.5.1 CompactPCI Connector J3, power and ground293.4.6 On-board Ethernet Indicator LEDs30Table 15. Compact PCI connector J3 pin out303.5 Mezzanine Card Sites323.5.1 PT5MC Type Mezzanine Cards323.5.2 PT2MC Type Mezzanine Cards323.5.3 PMC Type Mezzanine Cards323.5.4 Mezzanine Card Power333.5.5 PTMC/PMC Connector Summary33Table 16. Mezzanine Card Power Budget33Table 17. PTMC/PMC Connector Summary333.5.6 PTMC Jn1 and Jn2 PCI Connectors34Table 18. PTMC Jn1 and Jn2 Connector Pin Assignments343.5.7 PTMC Jn3 CT Bus Connector35Table 19. PTMC Configuration #2/#5 Pn3 Connector Pin Assignment353.5.8 PTMC Jn4 LAN/User I/O Connector363.5.8.1 PTMC Site A Jn436Table 20. PTMC Site A Configuration #2/#5 Pn4 Connector Pin Assignment373.5.8.2 PTMC Site B Pn438Table 21. PTMC Site B Configuration #2/#5 Pn4 Connector Pin Assignment383.5.9 PTMC Site Voltage Keying393.6 IPMI System Management393.6.1 IPMI Controller393.6.2 Temperature and Voltage Monitor40Figure 13. IPMI Block Diagram40Table 22. GPIO Port Assignments for IPMI403.6.3 Hot Swap Ejector Latch Detection413.6.4 Blue (Hot Swap) LED Control413.6.5 Boot Status Monitor41Table 23. Voltage Monitor A/D Port Assignments for IPMI41Table 24. HW400c/2 Temperature Sensor Locations413.6.6 Board Reset via IPMI423.6.7 IPMI System Power Supply423.6.8 IPMI Firmware EEPROMs42Table 25. Firmware EEPROM Addresses423.6.9 Zircon PM Reset433.6.10 IMPI Get Device ID43Table 26. Product ID number433.7 Hot Swap Support443.7.1 Hot Swap on J1 and J2443.7.2 Hot Swap on J3443.7.3 Hot Swap on J4443.7.4 Hot Swap on J5443.7.5 Hot Swap Sequence45Table 27. Overview of Hot Swap Insertion/Extraction Sequences454 Programming Information464.1 HW400c/2 Memory Map46Table 28. HW400c/2 Memory Map464.2 CPLD Registers47Table 29. CPLD Registers474.2.1 Clock Select Register (CSR)48Table 30. Clock Select Register (CSR) Offset Address 0x04484.2.2 Board Status Register (BSR)494.2.3 LED Register A (LEDA)49Table 31. Board Select Register (BSR) Offset Address 0x0549Table 32. LED Register A (LEDA) Offset Address 0x06494.2.4 Memory Option Register (MOR)504.2.5 Geographic Addressing Register (GAR)50Table 33. Memory Option Register (MOR) Offset Address 0x0750Table 34. Geographic Addressing Register (CSR) Offset Address 0x08504.2.6 PTMC Reset Register (PRR)514.2.7 PTMC Control Register (PCR)51Table 35. PTMC Reset Register (PRR) Offset Address 0x0951Table 36. PTMC Control Register (PCR) Offset Address 0x0A514.2.8 Board Option Register (BOR)524.2.9 General Purpose Register (GPR)52Table 37. Board Option Register (BOR) Offset Address 0x0D52Table 38. General Purpose Register (GPR) Offset Address 0x0E524.2.10 PCI Status Register (PSR)534.2.11 Extended Type Register (ETR)53Table 39. PCI Status Register (PSR) Offset Address 0x0F53Table 40. Extended Type Register (ETR) Offset Address 0x10534.2.12 Hardware Revision Register (HRR)544.2.13 PLL Configuration Register A (PLLA)54Table 41. Hardware Revision Register (HRR) Offset Address54Table 42. PLL Configuration Register A (PLLA) Offset Address 0x12544.2.14 PLL Configuration Register B (PLLB)55Table 43. PLL Configuration Register B (PLLB) Offset Address 0x13554.2.15 LED Register B (LEDB)56Table 44. LED Register B (LEDB) Offset Address 0x1456Table 45. On-board LED functions as determined by LEDB [1:0]564.2.16 Device Control Register (DCR)574.2.17 CPU Timer Register (CTR)57Table 46. Device Control Register (CSR) Offset Address 0x1557Table 47. CPU Timer Register (CTR) Offset Address 0x16574.2.18 Warm Reset Register (WRR)584.2.19 SPI Page Register (SPR)584.2.20 SPI Address Register (SAR)58Table 48. Warm Reset Register (WRR) Offset address 0x1758Table 49. SPI Page Register (SPR) Offset Address 0x1A58Table 50. SPI Address Register (SAR) Offset Address 0x1B584.2.21 SPI Read Byte Offset Register (SOR)594.2.22 Read Byte Count Register (RBC)59Table 51. SPI Read Byte Offset Select Register (SOR) Offset Address 0x1C59Table 52. Read Byte Count Register (RBC) Offset Address 0x1D594.2.23 Write Byte Count Register (WBC)604.2.24 SPI Data Registers (SDR0 – SDR7)60Table 53. Write Byte Count Register (WBC) Offset Address 0x1E60Table 54. SPI Data Registers (SDRn) Offset Address 0x20-0x27604.2.25 SPI Error and Status Register (SESR)614.2.26 EEPROM Address Register (EAR)61Table 55. SPI Error and Status Register (SESR) Offset Address 0x1F61Table 56. EEPROM Address Register (EAR) Offset Address 0x28614.2.27 EEPROM Operation/Status Register (EOSR)62Table 57. EEPROM Operation/Status Register (EOSR) Offset Address 0x29624.2.28 EEPROM Data Registers (EDR0 – EDR1)634.3 Accessing the Serial EEPROM634.3.1 Reading an EEPROM Address63Table 58. EEPROM Data Registers (EDRn) Offset Address 0x2A-0x2B634.3.2 Writing an EEPROM Address644.4 Accessing the SPI Interface644.4.1 Registers in the CPLD644.4.2 BCM5388 Registers Access Rules644.4.3 Reading BCM5388 Register654.4.4 Writing a BCM5388 Register655 Linux on the HW400c/2 and Host system675.1 Host Hardware and Software Requirements67Figure 14. HW400c/2 Network and System environment675.2 Network and System Configuration685.3 Installing Linux on your host system685.4 Configuring the Host System695.4.1 Modifying the Host Path695.4.2 Configuring the Host NFS Server695.4.3 Configuring Host tftp services705.4.4 Configuring tftp with inetd715.4.5 Configuring tftp with xinetd735.4.6 Configuring a bootp Server745.5 Booting the HW400c/2755.5.1 U-boot, Universal Bootloader765.5.1.1 U-boot commands765.5.1.2 U-boot environment variables775.5.1.3 Power up call trace795.5.2 Booting with tftp805.5.2.1 U-boot parameters for tftp with bootp805.5.2.2 U-boot parameters for tftp with static IP address815.5.2.3 Boot console815.5.3 Booting with Disk on Chip845.5.3.1 Loading the Disk on Chip845.5.3.2 Creating a uRamdisk Image855.5.3.3 Booting from DoC855.6 Compiling the Kernel (uImage)865.6.1 Gentoo Application Packages Management875.6.1.1 Emerge875.6.1.2 Enable remote login with ssh885.6.1.3 Starting network services; xinetd885.6.1.4 Starting ftp services; vsftpd885.7 Linux Device Drivers89Appendix A IPMI GetDeviceID90Appendix B U-Boot Environment variables91크기: 1.67메가바이트페이지: 104Language: English매뉴얼 열기