데이터 시트 (STEVAL-IME003V1)차례1 Schematic diagrams2Figure 1. STEVAL-IME003V1 hierarchical blocks2Figure 2. STEVAL-IME003V1 FPGA bank 0 configuration3Figure 3. STEVAL-IME003V1 FPGA bank 1 configuration4Figure 4. STEVAL-IME003V1 FPGA bank 2 configuration5Figure 5. STEVAL-IME003V1 FPGA bank 3 configuration6Figure 6. STEVAL-IME003V1 FPGA bank 3 configuration7Figure 7. STEVAL-IME003V1 FPGA power and configuration8Figure 8. STEVAL-IME003V1 configuration of the STHV7489Figure 9. STEVAL-IME003V1 configuration of the STM32102 Revision history11Table 1. Document revision history11크기: 251킬로바이트페이지: 12Language: English매뉴얼 열기
