데이터 시트 (CDCLVD1204EVM)차례Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board11 Features12 General Description13 Signal Path and Control Circuitry24 Getting Started25 Device Selection26 Power Supply Connection27 Input Clock Selection27.1 Configuring Single-Ended Input28 Output Clock29 The EVM Board Schematic310 Bill of Materials5Important Notices6크기: 211킬로바이트페이지: 7Language: English매뉴얼 열기
