데이터 시트 (CDCLVD2106EVM)차례Low Additive Jitter, Twelve LVDS Outputs Clock Buffer Evaluation Board11 Features12 General Description23 Signal Path and Control Circuitry24 Getting Started25 Device Selection26 Power Supply Connection27 Input Clock Selection27.1 Configuring Single-Ended Input28 Output Clock39 EVM Board Schematic and Bill of Materials39.1 EVM Board Schematic39.2 Bill of Materials6Important Notices7크기: 2.95메가바이트페이지: 8Language: English매뉴얼 열기
