사용자 설명서차례Table of Contents3Preface71 Overview91.1 Scope of the Standard101.1.1 Rules and Guidelines111.2 Requirements of the Standard111.3 Goals of the Standard121.4 Intentional Omissions121.5 System Architecture131.5.1 Frameworks131.5.2 Algorithms141.5.3 Core Run-Time Support142 General Programming Guidelines152.1 Use of C Language162.2 Threads and Reentrancy162.2.1 Threads162.2.2 Preemptive vs. Non-Preemptive Multitasking172.2.3 Reentrancy172.2.4 Example182.3 Data Memory192.3.1 Memory Spaces202.3.2 Scratch versus Persistent202.3.3 Algorithm versus Application222.4 Program Memory232.5 ROM-ability232.6 Use of Peripherals243 Algorithm Component Model253.1 Interfaces and Modules263.1.1 External Identifiers273.1.2 Naming Conventions283.1.3 Module Initialization and Finalization283.1.4 Module Instance Objects283.1.5 Design-Time Object Creation293.1.6 Run-Time Object Creation and Deletion293.1.7 Module Configuration303.1.8 Example Module303.1.9 Multiple Interface Support313.1.10 Interface Inheritance323.1.11 Summary323.2 Algorithms333.3 Packaging343.3.1 Object Code343.3.2 Header Files353.3.3 Debug Verses Release354 Algorithm Performance Characterization374.1 Data Memory384.1.1 Heap Memory384.1.2 Stack Memory394.1.3 Static Local and Global Data Memory394.2 Program Memory404.3 Interrupt Latency414.4 Execution Time414.4.1 MIPS Is Not Enough414.4.2 Execution Time Model425 DSP-Specific Guidelines455.1 CPU Register Types465.2 Use of Floating Point475.3 TMS320C6xxx Rules and Guidelines475.3.1 Endian Byte Ordering475.3.2 Data Models475.3.3 Program Model475.3.4 Register Conventions485.3.5 Status Register485.3.6 Interrupt Latency495.4 TMS320C54xx Rules and Guidelines495.4.1 Data Models495.4.2 Program Models495.4.3 Register Conventions515.4.4 Status Registers515.4.5 Interrupt Latency525.5 TMS320C55x Rules and Guidelines525.5.1 Stack Architecture525.5.2 Data Models525.5.3 Program Models535.5.4 Relocatability535.5.5 Register Conventions545.5.6 Status Bits555.6 TMS320C24xx Guidelines575.6.1 General575.6.2 Data Models575.6.3 Program Models575.6.4 Register Conventions575.6.5 Status Registers585.6.6 Interrupt Latency585.7 TMS320C28x Rules and Guidelines585.7.1 Data Models585.7.2 Program Models595.7.3 Register Conventions595.7.4 Status Registers595.7.5 Interrupt Latency606 Use of the DMA Resource616.1 Overview626.2 Algorithm and Framework626.3 Requirements for the Use of the DMA Resource636.4 Logical Channel636.5 Data Transfer Properties646.6 Data Transfer Synchronization646.7 Abstract Interface656.8 Resource Characterization666.9 Runtime APIs676.10 Strong Ordering of DMA Transfer Requests676.11 Submitting DMA Transfer Requests686.12 Device Independent DMA Optimization Guideline686.13 C6xxx Specific DMA Rules and Guidelines696.13.1 Cache Coherency Issues for Algorithm Producers696.14 C55x Specific DMA Rules and Guidelines706.14.1 Supporting Packed/Burst Mode DMA Transfers706.14.2 Minimizing Logical Channel Reconfiguration Overhead716.14.3 Addressing Automatic Endianism Conversion Issues716.15 Inter-Algorithm Synchronization716.15.1 Non-Preemptive System716.15.3 Preemptive System72A Rules and Guidelines75A.1 General Rules76A.2 Performance Characterization Rules77A.3 DMA Rules77A.4 General Guidelines78A.5 DMA Guidelines79B Core Run-Time APIs81B.1 TI C-Language Run-Time Support Library82B.2 DSP/BIOS Run-time Support Library82C Bibliography83C.1 Books83C.2 URLS83D Glossary85D.1 Glossary of Terms85크기: 603킬로바이트페이지: 88Language: English매뉴얼 열기