데이터 시트 (TPS65050EVM-195)차례1 Introduction11.1 Related Documentation From Texas Instruments12 Setup22.1 Input/Output Connector Descriptions22.1.1 J1 —VIN22.1.2 J2—GND22.1.3 J3—VDCDC122.1.4 J4—GND22.1.5 J5 —VDCDC222.1.6 J6—GND22.1.7 J7—VLDO122.1.8 J8—GND22.1.9 J9—VLDO222.1.10 J10—GND32.1.11 J11—VLDO332.1.12 J12 —GND32.1.13 J13 —VLDO432.1.14 J14—GND32.1.15 J15 —PB_OUT or RESET32.1.16 JP1 —EN VDCDC132.1.17 JP2 —MODE32.1.18 JP3 —DEFLDO132.1.19 JP4—DEFLDO232.1.20 JP5—DEFLDO342.1.21 JP6—DEFLDO442.1.22 JP7—EN VDCDC242.1.23 JP8 —DEFDCDC242.1.24 JP9 —EN LDO142.1.25 JP10 —EN LDO242.1.26 JP11—EN LDO342.1.27 JP12—EN LDO442.2 Setup52.2.1 EVM Family Configuration52.2.2 Operation53 Board Layout73.1 Layout74 Schematic and Bill of Materials124.1 Schematic124.2 Bill of Materials13Important Notices15크기: 411킬로바이트페이지: 16Language: English매뉴얼 열기
