Intel N450 AU80610004653AA Manual Do Utilizador
Códigos do produto
AU80610004653AA
Functional Description
26
Datasheet
3.1.3
Rules for populating SO-DIMM slots
The frequency of system memory will be the lowest frequency of all SO-DIMMs in the
system, as determined through the SPD registers on the SO-DIMMs. Timing
parameters [CAS latency (or CL + AL for DDR2), tRAS, tRCD, tRP] must be
programmed to match within a channel.
system, as determined through the SPD registers on the SO-DIMMs. Timing
parameters [CAS latency (or CL + AL for DDR2), tRAS, tRCD, tRP] must be
programmed to match within a channel.
To take advantage of enhanced addressing, it should be populating both SO-DIMM slots
with the identical Raw Card type. If one SO-DIMM is used only, it should be populating
the second slot (the further slot to the processor’s Integrated Memory Controller) to
get the best signal quality.
with the identical Raw Card type. If one SO-DIMM is used only, it should be populating
the second slot (the further slot to the processor’s Integrated Memory Controller) to
get the best signal quality.
3.1.4
Intel
®
Fast Memory Access (Intel
®
FMA) Technology
Enhancements
The following sections outline and explain the technology enhancements: Just-in-Time
Command Scheduling, Command Overlap, Out-of-Order Scheduling and Opportunistic
Writes.
Command Scheduling, Command Overlap, Out-of-Order Scheduling and Opportunistic
Writes.
3.1.4.1
Just-in-Time Command Scheduling
The memory controller has an advanced command scheduler where all pending
requests are examined simultaneously to determine the most efficient request to be
issued next. The most efficient request is picked from all pending requests and issued
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,
instead of having all memory access requests go individually through an arbitration
mechanism forcing requests to be executed one at a time, they can be started without
interfering with the current request allowing for concurrent issuing of requests. This
allows for optimized bandwidth and reduced latency while maintaining appropriate
command spacing to meet system memory protocol.
requests are examined simultaneously to determine the most efficient request to be
issued next. The most efficient request is picked from all pending requests and issued
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,
instead of having all memory access requests go individually through an arbitration
mechanism forcing requests to be executed one at a time, they can be started without
interfering with the current request allowing for concurrent issuing of requests. This
allows for optimized bandwidth and reduced latency while maintaining appropriate
command spacing to meet system memory protocol.
3.1.4.2
Command Overlap
Command Overlap allows the insertion of the DRAM commands between the Activate,
Precharge, and Read/Write commands normally used, as long as the inserted
commands do not affect the currently executing command. Multiple commands can be
issued in an overlapping manner, increasing the efficiency of system memory protocol.
Precharge, and Read/Write commands normally used, as long as the inserted
commands do not affect the currently executing command. Multiple commands can be
issued in an overlapping manner, increasing the efficiency of system memory protocol.
C
256MB
512Mb
32M x 16
4
1
8K
C
512MB
1Gb
64M x 16
4
1
8K
C
1GB
2Gb
128M x 16
4
1
8K
Table 3-16.Supported SO-DIMM Module Configurations (Sheet 2 of 2)
Raw Card
Tpye
DIMM
Capacity
DRAM
Device
Tech.
DRAM
Organization
# of DRAM
Devices
# of
Ranks
Page
Size