Intel SL2YM Manual Do Utilizador
Pentium
®
II Processor at 350 MHz, 400 MHz, and 450 MHz
16
Datasheet
To ensure the system is ready for current and future Pentium II processors, the range of values in
bold in
bold in
Table 1
must be supported. A smaller range will risk the ability of the system to migrate to
a higher performance Pentium II processor and/or maintain compatibility with current Pentium II
processors.
processors.
NOTES:
1. 0 = Processor pin connected to V
SS
.
2. 1 = Open on processor; may be pulled up to TTL V
IH
on motherboard.
3. VRM output should be disabled for V
CC
CORE
values less than 1.80 V.
4. To ensure the system is ready for the Pentium
®
II processors, the values in BOLD in
Table 1
must be supported.
Note that the ‘11111’ (all opens) ID can be used to detect the absence of a processor core in a given
slot as long as the power supply used does not affect these lines. Detection logic and pull-ups
should not affect VID inputs at the power source (see
slot as long as the power supply used does not affect these lines. Detection logic and pull-ups
should not affect VID inputs at the power source (see
Section 7.0
).
The VID pins should be pulled up to a TTL-compatible level with external resistors to the power
source of the regulator only if required by the regulator or external logic monitoring the VID[4:0]
signals. The power source chosen must be guaranteed to be stable whenever the supply to the
voltage regulator is stable. This will prevent the possibility of the processor supply going above the
specified V
source of the regulator only if required by the regulator or external logic monitoring the VID[4:0]
signals. The power source chosen must be guaranteed to be stable whenever the supply to the
voltage regulator is stable. This will prevent the possibility of the processor supply going above the
specified V
CC
CORE
in the event of a failure in the supply for the VID lines. In the case of a DC-to-DC
converter, this can be accomplished by using the input voltage to the converter for the VID line
Table 1.
Voltage Identification Definition
1, 2, 3
Processor Pins
VID4
VID3
VID2
VID1
VID0
V
CC
CORE
01111 - 00110
Reserved
0
0
1
0
1
1.80
4
0
0
1
0
0
1.85
4
0
0
0
1
1
1.90
4
0
0
0
1
0
1.95
4
0
0
0
0
1
2.00
4
0
0
0
0
0
2.05
4
1
1
1
1
1
No Core
1
1
1
1
0
2.1
4
1
1
1
0
1
2.2
4
1
1
1
0
0
2.3
4
1
1
0
1
1
2.4
4
1
1
0
1
0
2.5
4
1
1
0
0
1
2.6
4
1
1
0
0
0
2.7
4
1
0
1
1
1
2.8
4
1
0
1
1
0
2.9
1
0
1
0
1
3.0
1
0
1
0
0
3.1
1
0
0
1
1
3.2
1
0
0
1
0
3.3
1
0
0
0
1
3.4
1
0
0
0
0
3.5