Renesas SH7709S Manual Do Utilizador
Rev. 5.00, 09/03, page 82 of 760
VPN
31
23
11110010
*
*
16
(1) TLB Address Array Access
Read access
W
0
*
VPN
*
31
23
24
24
17
17
17
11110010
*
*
*
*
16
Write access
Read/write access
W
6
0
*
*
0
VPN
31
23
24
11110011
000
*
*
16
17
Address field
W
0
*
*
31
29 28
Data field
10
PPN
8
9
7 6 5 4
3 2
1
0
X
V
X
X
VPN
31
16
Data field
(2) TLB Data Array Access
12
10
11
8
9
7
12
10
11
8
9
7
12
10
11
8
9
7
12
10
11
8
9
7
6
*
0
0
ASID
0 V
VPN
0
0
17
VPN
16
12
10
11
VPN
31
ASID
8
9
7
0
* V
D
C
SH
PR SZ
VPN:
V:
W:
Virtual page number
Valid bit
Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
Valid bit
Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
ASID:
:
Address space identifier
Don't care bit
Don't care bit
PPN:
PR:
C:
SH:
VPN:
X:
W:
Physical page number
Protection key field
Cacheable bit
Share status bit
Virtual page number
0 for read, don’t care bit for write
Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
Protection key field
Cacheable bit
Share status bit
Virtual page number
0 for read, don’t care bit for write
Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
V:
SZ:
D:
:
Valid bit
Page-size bit
Dirty bit
Don't care bit
Page-size bit
Dirty bit
Don't care bit
Address field
Data field
Address field
*
*
*
* *
* *
Figure 3.14 Specifying Address and Data for Memory-Mapped TLB Access