Renesas SH7709S Manual Do Utilizador
Rev. 5.00, 09/03, page 107 of 760
31
9
8
7
2
1
0
W2
LOAD
W3
LOCK
W3
LOAD
W2
LOCK
W2LOCK: Way 2 lock bit. W2LOAD: Way 2 load bit.
When W2LOCK = 1 & W2LOAD = 1 & SR, CL = 1, the prefetched data will always be
loaded into Way2. In all other conditions the prefetched data will be loaded into the way
pointed by LRU.
loaded into Way2. In all other conditions the prefetched data will be loaded into the way
pointed by LRU.
W3LOCK: Way 3 lock bit. W3LOAD: Way 3 load bit.
When W3LOCK = 1 & W3LOAD = 1 & SR, CL = 1, the prefetched data will always be
loaded into Way3. In all other conditions the prefetched data will be loaded into the way
pointed by LRU.
Note: W2LOAD and W3LOAD should not be set to high at the same time.
loaded into Way3. In all other conditions the prefetched data will be loaded into the way
pointed by LRU.
Note: W2LOAD and W3LOAD should not be set to high at the same time.
—: Reserved bits.
Figure 5.3 CCR2 Register Configuration
Whenever CCR2 bit 8 (W3LOCK) or bit 0 (W2LOCK) is high the cache is locked. The locked
data will not be overwritten unless W3LOCK bit and W2LOCK bit are reset or the PREF
condition during DSP mode matched. During cache locking mode, the LRU in table 5.2 will be
replaced by tables 5.4 to 5.8.
data will not be overwritten unless W3LOCK bit and W2LOCK bit are reset or the PREF
condition during DSP mode matched. During cache locking mode, the LRU in table 5.2 will be
replaced by tables 5.4 to 5.8.
Table 5.4
Way Replacement when PREF Instruction Ended Up in a Cache Miss
DSP bit
W3LOAD
W3LOCK
W2LOAD
W2LOCK
Way to be replaced
0
*
*
*
*
Depends on LRU (table 5.2)
1
*
0
*
0
Depends on LRU (table 5.2)
1
*
0
0
1
Depends on LRU (table 5.6)
1
0
1
*
0
Depends on LRU (table 5.7)
1
0
1
0
1
Depends on LRU (table 5.8)
1
0
*
1
1
Way 2
1
1
1
0
*
Way 3
*
: Don't care
Do not set as W3LOAD=1 and also W2LOAD=1