Renesas SH7709S Manual Do Utilizador
Rev. 5.00, 09/03, page 123 of 760
Table 6.3
IIIIR
R
R
RL
LL
L3333–IIIIR
R
R
RL
LL
L0000/IIIIR
R
R
RL
LL
LSSSS3333–IIIIR
R
R
RL
LL
LSSSS0000 Pins and Interrupt Levels
IIIIR
R
R
RL3
L3
L3
L3////
IIIIR
R
R
RLLLLS
S
S
S3333
IIIIR
R
R
RL2
L2
L2
L2////
IIIIR
R
R
RLLLLS
S
S
S2222
IIIIR
R
R
RL1
L1
L1
L1////
IIIIR
R
R
RLLLLS
S
S
S1111
IIIIR
R
R
RL0
L0
L0
L0////
IIIIR
R
R
RLLLLS
S
S
S0000
Interrupt Priority Level
Interrupt Request
0
0
0
0
15
Level 15 interrupt request
0
0
0
1
14
Level 14 interrupt request
0
0
1
0
13
Level 13 interrupt request
0
0
1
1
12
Level 12 interrupt request
0
1
0
0
11
Level 11 interrupt request
0
1
0
1
10
Level 10 interrupt request
0
1
1
0
9
Level 9 interrupt request
0
1
1
1
8
Level 8 interrupt request
1
0
0
0
7
Level 7 interrupt request
1
0
0
1
6
Level 6 interrupt request
1
0
1
0
5
Level 5 interrupt request
1
0
1
1
4
Level 4 interrupt request
1
1
0
0
3
Level 3 interrupt request
1
1
0
1
2
Level 2 interrupt request
1
1
1
0
1
Level 1 interrupt request
1
1
1
1
0
No interrupt request
A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels
sampled at every peripheral module clock cycle remain unchanged for two consecutive cycles, so
that no transient level on the
sampled at every peripheral module clock cycle remain unchanged for two consecutive cycles, so
that no transient level on the
IRL/IRLS pin change is detected. In standby mode, as the peripheral
clock is stopped, noise cancellation is performed using the 32-kHz clock for the RTC instead.
Therefore when the RTC is not used, interruption by means of IRL interrupts cannot be performed
in standby mode.
Therefore when the RTC is not used, interruption by means of IRL interrupts cannot be performed
in standby mode.
The priority level of the IRL interrupt must not be lowered until the interrupt is accepted and
interrupt handling starts. Correct operation cannot be guaranteed if the level is not maintained.
However, the priority level can be changed to a higher one.
interrupt handling starts. Correct operation cannot be guaranteed if the level is not maintained.
However, the priority level can be changed to a higher one.
The interrupt mask bits (I3–I0) in the status register (SR) are not affected by
IRL/IRLS interrupt
handling.
When the interrupt level of the IRL interrupt is higher than the level set by the I3-I0 bits in the SR,
the IRL interrupt can be used to recover from standby mode (however, this only applies when the
RTC is used for 32-kHz oscillator).
the IRL interrupt can be used to recover from standby mode (however, this only applies when the
RTC is used for 32-kHz oscillator).