Renesas SH7709S Manual Do Utilizador

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Rev. 5.00, 09/03, page 195 of 760
Standby to Power-On Reset
CKIO, CKIO2
*
7
STATUS
Normal
*
5
Normal
*
5
Oscillation stops
Standby
*
4
0 to 10 Bcyc
*
6
0 to 30 Bcyc
*
6
Reset
Reset
*
3
RESETP*
1
*
2
Notes:  1.  When standby mode is cleared with a power-on reset, the WDT does not 
  
count. 
Keep 
RESETP low during the PLL’s oscillation settling time.
 2. 
Undefined
 
3.  Reset: 
HH (STATUS1 high, STATUS0 high)
 
4.  Standby:  LH (STATUS1 low, STATUS0 high)
 
5.  Normal:  LL (STATUS1 low, STATUS0 low)
 
6.  Bcyc: 
Bus clock cycle
 
7.  The CKIO2 output is available only in clock modes 0, 1, and 2.
Figure 8.5   Standby to Power-On Reset STATUS Output