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Renesas SH7709S Manual Do Utilizador

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Rev. 5.00, 09/03, page 251 of 760
Bits 9, 3, and 2—Area 5 
O
O
O
OE
EE
E/W
W
W
WE
EE
E Negate Address Delay (A5TEH2, A5TEH1, A5TEH0):
Specify the address hold delay time from 
OE/WE negation for the PCMCIA interface connected to
area 5.
Bit 9:
A5TEH2
Bit 3:
A5TEH1
Bit 2:
A5TEH0
Description
0
0
0
0.5-cycle  delay 
(Initial  value)
1
1.5-cycle delay
1
0
2.5-cycle  delay
1
3.5-cycle delay
1
0
0
4.5-cycle  delay
1
5.5-cycle delay
1
0
6.5-cycle  delay
1
7.5-cycle delay
Bits 8, 1, and 0—Area 6 
O
O
O
OE
EE
E/W
W
W
WE
EE
E Negate Address Delay (A6TEH2, A6TEH1, A6TEH0):
Specify the address hold delay time from 
OE/WE negation for the PCMCIA interface connected to
area 6.
Bit 8:
A6TEH2
Bit 1:
A6TEH1
Bit 0:
A6TEH0
Description
0
0
0
0.5-cycle  delay 
(Initial  value)
1
1.5-cycle delay
1
0
2.5-cycle  delay
1
3.5-cycle delay
1
0
0
4.5-cycle  delay
1
5.5-cycle delay
1
0
6.5-cycle  delay
1
7.5-cycle delay