Renesas SH7709S Manual Do Utilizador
Rev. 5.00, 09/03, page 263 of 760
Table 10.10 32-Bit External Device/Little-Endian Access and Data Alignment
Data Bus
Strobe Signals
Operation
D31–D24
D23–D16
D15–D8
D7–D0
W
W
W
WE
EE
E3333
,
DQMUU
W
W
W
WE
EE
E2222
,
DQMUL
W
W
W
WE
EE
E1111
,
DQMLU
W
W
W
WE
EE
E0000
,
DQMLL
Byte access
at 0
at 0
—
—
—
Data
7–0
7–0
Asserted
Byte access
at 1
at 1
—
—
Data
7–0
7–0
—
Asserted
Byte access
at 2
at 2
—
Data
7–0
7–0
—
—
Asserted
Byte access
at 3
at 3
Data
7–0
7–0
—
—
—
Asserted
Word access
at 0
at 0
—
—
Data
15–8
15–8
Data
7–0
7–0
Asserted
Asserted
Word access
at 2
at 2
Data
15–8
15–8
Data
7–0
7–0
—
—
Asserted
Asserted
Longword
access at 0
access at 0
Data
31–24
31–24
Data
23–16
23–16
Data
15–8
15–8
Data
7–0
7–0
Asserted
Asserted
Asserted
Asserted
Table 10.11 16-Bit External Device/Little-Endian Access and Data Alignment
Data Bus
Strobe Signals
Operation
D31–
D24
D24
D23–
D16
D16
D15–D8
D7–D0
W
W
W
WE
EE
E3333
,
DQMUU
W
W
W
WE
EE
E2222
,
DQMUL
W
W
W
WE
EE
E1111
,
DQMLU
W
W
W
WE
EE
E0000
,
DQMLL
Byte access at 0
—
—
—
Data
7–0
7–0
Asserted
Byte access at 1
—
—
Data
7–0
7–0
—
Asserted
Byte access at 2
—
—
—
Data
7–0
7–0
Asserted
Byte access at 3
—
—
Data
7–0
7–0
—
Asserted
Word access at 0
—
—
Data
15–8
15–8
Data
7–0
7–0
Asserted
Asserted
Word access at 2
—
—
Data
15–8
15–8
Data
7–0
7–0
Asserted
Asserted
1st time
at 0
at 0
—
—
Data
15–8
15–8
Data
7–0
7–0
Asserted
Asserted
Longword
access
at 0
access
at 0
2nd time
at 2
at 2
—
—
Data
31–24
31–24
Data
23–16
23–16
Asserted
Asserted