Renesas SH7709S Manual Do Utilizador
Rev. 5.00, 09/03, page 378 of 760
Bit 0—Count Start 0 (STR0): Selects whether to operate or halt CMCNT0.
Bit 0: STR0
Description
0
CMCNT0 count operation halted
(Initial value)
1
CMCNT0 count operation
Compare Match Timer Control/Status Register 0 (CMCSR0)
The compare match timer control/status register 0 (CMCSR0) is a 16-bit register that indicates the
occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the
clock used for incrementation. It is initialized to H'0000 by a reset, but retains its previous value in
standby mode.
occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the
clock used for incrementation. It is initialized to H'0000 by a reset, but retains its previous value in
standby mode.
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
CMF
—
—
—
—
—
CKS1
CKS0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/(W)
*
R/W
R
R
R
R
R/W
R/W
Note:
*
The only value that can be written is 0 to clear the flag.
Bits 15 to 8 and 5 to 2—Reserved: These bits are always read as 0. The write value should
always be 0.
always be 0.
Bit 7—Compare Match Flag (CMF): Indicates whether or not the compare match timer counter
0 (CMCNT0) and compare match timer constant 0 (CMCOR0) values match.
0 (CMCNT0) and compare match timer constant 0 (CMCOR0) values match.
Bit 7: CMF
Description
0
CMCNT0 and CMCOR0 values do not match
(Initial value)
Clearing condition: Write 0 to CMF after reading CMF = 1
1
CMCNT0 and CMCOR0 values match