Renesas SH7709S Manual Do Utilizador
Rev. 5.00, 09/03, page 382 of 760
CK
CMCOR0
CMCNT0
input clock
Compare
match signal
CMF
CMI
CMCNT0
N
N
0
Figure 11.27 CMF Setting Timing
Compare Match Flag Clearing Timing
The CMF bit in the CMCSR0 register is cleared by writing 0 to it after reading 1. Figure 11.28
shows the timing when the CMF bit is cleared by the CPU.
shows the timing when the CMF bit is cleared by the CPU.
CK
CMF
CMCSR0 write cycle
T
1
T
2
Figure 11.28 Timing of CMF Clearing by the CPU