Renesas SH7709S Manual Do Utilizador

Rev. 5.00, 09/03, page 441 of 760

Bit 6—Receive Data Register Full (RDRF): Indicates that SCRDR contains received data.

0

SCRDR does not contain valid receive data

(Initial value)

[Clearing conditions]

(1) RDRF is cleared to 0 when the chip is reset or enters standby mode.

(2) Software reads RDRF after it has been set to 1, then writes 0 in RDRF.

1

SCRDR contains valid receive data

[Setting condition]

RDRF is set to 1 when serial data is received normally and transferred from
SCRSR to SCRDR.

Note:

SCRDR and RDRF are not affected by detection of receive errors or by clearing of the RE
bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set
to 1 when reception of the next data ends, an overrun error (ORER) occurs and the receive
data is lost.

Bit 5—Overrun Error (ORER): Indicates that data reception aborted due to an overrun error.

0

Receiving is in progress or has ended normally

*

1

(Initial value)

[Clearing conditions]

(1) ORER is cleared to 0 when the chip is reset or enters standby mode.

(2) When software reads ORER after it has been set to 1, then writes 0 to

ORER.

1

A receive overrun error occurred

*

2

[Setting condition]

ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1.

Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which

retains its previous value.

2. SCRDR continues to hold the data received before the overrun error, so subsequent

receive data is lost. Serial receiving cannot continue while ORER is set to 1. In
synchronous mode, serial transmitting is also disabled.