Renesas SH7709S Manual Do Utilizador
Rev. 5.00, 09/03, page 487 of 760
The receive margin in asynchronous mode can therefore be expressed as in equation 1.
Equation 1:
M = 0.5
−
1
2N
D
−
0.5
N
−
(L
−
0.5)F
−
(1 + F)
×
100%
Where:
M
=
Receive margin (
%
)
N
=
Ratio of clock frequency to bit rate (N
=
16)
D
=
Clock duty cycle (D
=
0 to 1.0)
L
=
Frame length (L
=
9 to 12)
F
=
Absolute deviation of clock frequency
From equation 1, if F
=
0 and D
=
0.5, the receive margin is 46.875%, as in equation 2.
Equation 2:
M
=
(0.5 – 1/(2
×
16))
×
100
%
=
46.875
%
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Notes on Synchronous External Clock Mode:
•
Do not set TE
=
RE
=
1 until at least four clocks after external clock SCK has changed from 0
to 1.
•
Set TE
=
RE
=
1 only when external clock SCK is 1.
•
When receiving, RDRF is set to 1 when RE is set to zero 2.5–3.5 clocks after the rising edge of
the SCK input of the D7 bit in RxD, but data cannot be copied to SCRDR.
the SCK input of the D7 bit in RxD, but data cannot be copied to SCRDR.
Note on Synchronous Internal Clock Mode: When receiving, RDRF is set to 1 when RE is cleared
to zero 1.5 clocks after the rising edge of the SCK output of the D7 bit in RxD, but data cannot be
copied to SCRDR.
to zero 1.5 clocks after the rising edge of the SCK output of the D7 bit in RxD, but data cannot be
copied to SCRDR.