Renesas SH7709S Manual Do Utilizador

Rev. 5.00, 09/03, page 492 of 760

This section describes the registers added for the smart card interface and the bits whose functions
are changed.

The smart card mode register (SCSCMR) is an 8-bit readable/writable register that selects smart
card interface functions. SCSCMR bits 0, 2, and 3 are initialized to H'00 by a reset and in standby
mode.

Bit:

7

6

5

4

3

2

1

0

—

—

—

—

SDIR

SINV

—

SMIF

Initial  value:

—

—

—

—

0

0

—

0

R/W:

R

R

R

R

R/W

R/W

R

R/W

Bits 7 to 4 and 1—Reserved: These bits are always read as 0. The write value should always be
0.

Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion
format.

0

Contents of SCTDR are transferred LSB-first, and receive data is stored in
SCRDR LSB-first

(Initial value)

1

Contents of SCTDR are transferred MSB-first, and receive data is stored in
SCRDR MSB-first

Bit 2—Smart Card Data Inversion (SINV): Specifies whether to invert the logic level of the
data. This function is used in combination with bit 3 for transmitting and receiving with an inverse
convention card. SINV does not affect the logic level of the parity bit. See section 15.3.4, Register
Settings, for information on how parity is set.

0

Contents of SCTDR are transferred unchanged, and receive data is stored
in SCRDR unchanged

(Initial value)

1

Contents of SCTDR are inverted before transfer, and receive data is
inverted before storage in SCRDR