Renesas SH7709S Manual Do Utilizador
Rev. 5.00, 09/03, page 680 of 760
CKIO
A25 to A4
A3 to A0
CSn
RD/
WR
RD
D31 to D0
BS
DACKn
WAIT
T
1
T
w
T
w
T
B2
T
B1
T
2
T
Bw
t
AD
t
AD
t
CSD1
t
CSD2
t
RWD
t
RWH
t
RDH1
t
AH
t
AH
t
RWD
t
RSD
t
RSD1
t
AH
t
AD
t
BSD
t
BSD
t
WTS
t
WTH
t
WTS
t
WTH
t
WTS
t
WTH
t
WTS
t
WTH
t
BSD
t
BSD
t
RDS1
t
RDH1
t
RSD
t
DAKD1
t
DAKD2
t
RDH1
t
RWH
t
RSD1
t
RDS
Note: In the write cycle, the basic bus cycle is performed.
Figure 23.21 Burst ROM Bus Cycle (External Wait, WAITSEL = 1)