Renesas SH7709S Manual Do Utilizador
Rev. 5.00, 09/03, page 683 of 760
CKIO
A12 or A10
RD/
WR
CSn
RAS
CAS
BS
DQMxx
CKE
(High)
A25 to A16
A15 to A0
Tr
Tc1
Tc2/Td1 Tc3/Td2
Tc4/Td3
Td4
(Tpc)
(Tpc)
D31 to D0
Row address
Row
address
address
Read A
command
command
Read command
Row
address
address
Column address (1-4)
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tCSD3
tCSD3
tRWD
tRWD
tRASD2
tDQMD
tBSD
tBSD
tRDS2 tRDH2
tRDS2 tRDH2
tDQMD
tRASD2
tCASD2
tCASD2
tDAKD1
tDAKD1
DACKn
Figure 23.24 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read
××××
4), RCD
====
0,
CAS Latency
====
1, TPC
====
1)