Renesas SH7709S Manual Do Utilizador
Rev. 5.00, 09/03, page 697 of 760
Tpc
TRa1
(TRs2)
(TRs2)
TRs3
CKIO
CKE
CSn
RAS
CAS
RD/
WR
t
RWD
t
RWD
t
CASD2
t
RASD2
t
CSD3
t
CASD2
t
CSD3
t
RASD2
Tp
t
CSD3
t
CSD3
t
RASD2
t
RASD2
(Tpc)
(Tpc)
t
CKED
t
CKED
t
RWD
Figure 23.38 Synchronous DRAM Self-Refresh Cycle (TRAS
====
1, TPC
====
1)