Renesas SH7709S Manual Do Utilizador

Rev. 5.00, 09/03, page 722 of 760

CKIO2/PTG[4]

129

L16

I/O

System clock output / input port

AUDATA[3]/
PTG[3]

130

L17

I

AUD data / input port

AUDATA[2]/
PTG[2]

131

K18

I

AUD data / input port

AUDATA[1]/
PTG[1]

133

K19

I

AUD data / input port

AUDATA[0]/
PTG[0]

135

J18

I

AUD data / input port

TRST

/PTF[7]/

PINT[15]

136

J19

I

Test reset / input port / port interrupt
request

TMS/PTF[6]/
PINT[14]

137

H16

I

Test mode switch / input port / port
interrupt request

TDI/PTF[5]/
PINT[13]

138

H17

I

Test data input / input port / port
interrupt request

TCK/PTF[4]/
PINT[12]

139

H18

I

Test clock / input port / port interrupt
request

IRLS

[3:0]/

PTF[3:0]/
PINT[11:8]

140 to 143

H19, G16,
G17, G18

I

External interrupt request / input port
/ port interrupt request

AUDCK/PTH[6]

151

D16

I

AUD clock / input port

WAIT

123

M19

I

Hardware wait request

BREQ

122

N16

I

Bus request

BACK

121

N17

O

Bus acknowledge

IRQOUT

160

A16

O

Interrupt / refresh request output

RESETP

193

C7

I

Power-on reset input

NMI

7

C3

I

Nonmaskable interrupt request

IRQ[3:0]/

IRL[3:0]

/

PTH[3:0]

11 to 8

F2, F1, E4, E3

I

External interrupt request / external
interrupt source / input port

IRQ4/PTH[4]

12

F3

I

External interrupt request / input port

CTS2

/IRQ5/

SCPT[7]

176

A11

I

Serial port 2 transfer enable /
external interrupt request / input port

TCLK/PTH[7]

159

B15

I/O

Clock I/O (for TMU/RTC) / I/O port

EXTAL

156

D18

I

External clock / crystal oscillator pin

XTAL

155

C18

O

Crystal oscillator pin

CAP1

146

F17

—

External capacitance pin (for PLL1)

CAP2

149

E16

—

External capacitance pin (for PLL2)