Renesas SH7709S Manual Do Utilizador

Rev. 5.00, 09/03, page 36 of 760

21

MUL

Double-precision multiplication (32 

×

 32

bits)

33

Arithmetic
operations
(cont)

MULS

Signed multiplication (16 

×

 16 bits)

MULU

Unsigned multiplication (16 

×

 16 bits)

NEG

Negation

NEGC

Negation with borrow

SUB

Binary subtraction

SUBC

Binary subtraction with borrow

SUBV

Binary subtraction with underflow check

6

AND

Logical AND

14

Logic
operations

NOT

Bit inversion

OR

Logical OR

TAS

Memory test and bit set

TST

Logical AND and T bit set

XOR

Exclusive OR

Shift

12

ROTL

One-bit left rotation

16

ROTR

One-bit right rotation

ROTCL

One-bit left rotation with T bit

ROTCR

One-bit right rotation with T bit

SHAL

One-bit arithmetic left shift

SHAR

One-bit arithmetic right shift

SHLL

One-bit logical left shift

SHLLn

n-bit logical left shift

SHLR

One-bit logical right shift

SHLRn

n-bit logical right shift

SHAD

Dynamic arithmetic shift

SHLD

Dynamic logical shift