Philips S1D13505 Manual Do Utilizador
Page 12
Epson Research and Development
Vancouver Design Center
S1D13505
Interfacing to the PC Card Bus
X23A-G-005-06
Issue Date: 01/02/05
3.2 PC Card Host Bus Interface Signals
The S1D13505 PC Card host bus interface is designed to support processors which
interface the S1D13505 through the PC Card bus.
interface the S1D13505 through the PC Card bus.
The S1D13505 PC Card host bus interface requires the following signals from the PC Card
bus.
bus.
• BUSCLK is a clock input which is required by the S1D13505 host bus interface. It is
separate from the input clock (CLKI) and is typically driven by the host CPU system
clock. Since PC Card signalling is independent of any clock, BUSCLK can come from
any oscillator already implemented. For example, the source for the CLKI input of the
S1D13505 may be used.
clock. Since PC Card signalling is independent of any clock, BUSCLK can come from
any oscillator already implemented. For example, the source for the CLKI input of the
S1D13505 may be used.
• The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the PC
Card address (A[20:0]) and data bus (D[15:0]), respectively. MD4 must be set to select
little endian mode upon reset.
little endian mode upon reset.
• M/R# (memory/register) selects between memory or register access. It may be
connected to an address line, allowing system address A21 to be connected to the M/R#
line.
line.
• Chip Select (CS#) must be driven low whenever the S1D13505 is accessed by the PC
Card bus.
• WE1# and RD/WR# connect to -CE2 and -CE1 (the byte enables for the high-order and
low-order bytes). They are driven low when the PC Card bus is accessing the
S1D13505.
S1D13505.
• RD# connects to -OE (the read enable signal from the PC Card bus).
• WE0# connects to -WE (the write enable signal from the PC Card bus).
• WAIT# is a signal output from the S1D13505 that indicates the PC Card bus must wait
until data is ready (read cycle) or accepted (write cycle) on the host bus. Since PC Card
bus accesses to the S1D13505 may occur asynchronously to the display update, it is
possible that contention may occur in accessing the S1D13505 internal registers and/or
display buffer. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete. For PC Card applications, this signal should
be set active low using the MD5 configuration input.
bus accesses to the S1D13505 may occur asynchronously to the display update, it is
possible that contention may occur in accessing the S1D13505 internal registers and/or
display buffer. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete. For PC Card applications, this signal should
be set active low using the MD5 configuration input.
• The Bus Start (BS#) signal is not used for the PC Card host bus interface and should be
tied high (connected to V
DD
).
• The RESET# (active low) input of the S1D13505 may be connected to the PC Card
RESET (active high) using an inverter.