Philips S1D13505 Manual Do Utilizador
Epson Research and Development
Page 13
Vancouver Design Center
Interfacing to the Motorola MPC821 Microprocessor
S1D13505
Issue Date: 01/02/05
X23A-G-008-05
3 S1D13505 Host Bus Interface
The S1D13505 implements a 16-bit native PowerPC host bus interface which is used to
interface to the MPC821 microprocessor.
interface to the MPC821 microprocessor.
The PowerPC host bus interface is selected by the S1D13505 on the rising edge of
RESET#. After releasing reset the bus interface signals assume their selected configuration.
For details on S1D13505 configuration, see Section 4.3, “S1D13505 Hardware Configu-
ration” on page 18.
RESET#. After releasing reset the bus interface signals assume their selected configuration.
For details on S1D13505 configuration, see Section 4.3, “S1D13505 Hardware Configu-
ration” on page 18.
Note
At reset, the Host Interface Disable bit in the Miscellaneous Disable Register
(REG[1Bh] bit 7) is set to 1. This means that only REG[1Ah] (read-only) and
REG[1Bh] are accessible until a write to REG[1Bh] sets bit 7 to 0 making all regis-
ters accessible. When debugging a new hardware design, this can sometimes give the
appearance that the interface is not working, so it is important to remember to clear this
bit before proceeding with debugging.
(REG[1Bh] bit 7) is set to 1. This means that only REG[1Ah] (read-only) and
REG[1Bh] are accessible until a write to REG[1Bh] sets bit 7 to 0 making all regis-
ters accessible. When debugging a new hardware design, this can sometimes give the
appearance that the interface is not working, so it is important to remember to clear this
bit before proceeding with debugging.
3.1 PowerPC Host Bus Interface Pin Mapping
The following table shows the functions of each host bus interface signal.
Table 3-1: PowerPC Host Bus Interface Pin Mapping
S1D13505
Pin Names
PowerPC
AB[20:0]
A[11:31]
DB[15:0]
D[0:15]
WE1#
BI
M/R#
External Decode
CS#
External Decode
BUSCLK
CLKOUT
BS#
TS
RD/WR#
RD/WR
RD#
TSIZ0
WE0#
TSIZ1
WAIT#
TA
RESET#
RESET#