Soyo SY-K7VEMPRO Manual Do Utilizador
BIOS Setup Utility
SY-K7VEMPRO
60
After you have completed the changes, press [Esc] and follow the
instructions on your screen to save your settings or exit without saving.
The following table describes each field in the Advanced Chipset Features
Menu and how to configure each parameter.
instructions on your screen to save your settings or exit without saving.
The following table describes each field in the Advanced Chipset Features
Menu and how to configure each parameter.
3-3.1 CHIPSET FEATURES SETUP
CHIPSET
FEATURES
FEATURES
Setting
Description
Note
Enabled
Default
DRAM
Timing By
SPD
Timing By
SPD
Disabled
If enable the DRAM will auto
detect the DRAM timing.
detect the DRAM timing.
DRAM Clock
133M
This item allows you to control the
DRAM speed.
DRAM speed.
default
SDRAM Cycle
Length
Length
3
2
2
When synchronous DRAM is
installed, the number of clock
cycles of CAS latency depends on
the DRAM timing. Do not reset
this field from the default value
specified by the system designer.
installed, the number of clock
cycles of CAS latency depends on
the DRAM timing. Do not reset
this field from the default value
specified by the system designer.
Default
4 Bank
Disabled
Default
Bank
Interleave
Interleave
2 Bank
Increase DRAM performance.
Disabled
Enabled
Disabled/Enabled PCI Master
Pipeline Req.
Pipeline Req.
Default
PCI Master
Pipeline Req
Pipeline Req
Disabled
Default
Memory Hole
15M – 16M Some interface cards will map
their ROM address to this area. If
this occurs, select [Enabled] in this
field.
this occurs, select [Enabled] in this
field.
Disabled
Default
P2C/C2P
Concurrency
Concurrency
Enabled
This item allows you to
enable/disable the PCI to CPU,
CPU to PCI concurrency
enable/disable the PCI to CPU,
CPU to PCI concurrency