Cypress CY7C1548V18 Manual Do Utilizador
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
CY7C1548V18, CY7C1550V18
Document Number: 001-06550 Rev. *E
Page 3 of 28
Logic Block Diagram (CY7C1548V18)
Logic Block Diagram (CY7C1550V18)
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
R
ead Add. Decode
Read Data Reg.
R/W
DQ
[17:0]
Output
Logic
Reg.
Reg.
Reg.
18
18
36
18
BWS
[1:0]
V
REF
W
rite Add. Decode
18
18
LD
Control
21
2M x 18
Array
2M x 18 Arr
a
y
Write
Reg
Reg
Write
Reg
Reg
CQ
CQ
R/W
DOFF
QVLD
18
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
Re
ad Add. Decode
Read Data Reg.
R/W
DQ
[35:0]
Output
Logic
Reg.
Reg.
Reg.
36
36
72
36
BWS
[3:0]
V
REF
W
rite Add. Decode
36
36
LD
Control
20
1M x 36 Ar
ray
1M x
36 Array
Write
Reg
Reg
Write
Reg
Reg
CQ
CQ
R/W
DOFF
QVLD
36