Cypress CY8C24223A Manual Do Utilizador

Document Number: 3-12029  Rev. *E

Page 25 of 31

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C 

≤ T

A

 

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only. 

All Functions

Maximum Block Clocking Frequency

24.96

MHz

Timer

Capture Pulse Width

50

a

a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

–

–

ns

Maximum Frequency, No Capture

–

–

24.96

MHz

4.75V < Vdd < 5.25V

Maximum Frequency, With Capture

–

–

24.96

MHz

Counter

Enable Pulse Width

50

a

–

–

ns

Maximum Frequency, No Enable Input

–

–

24.96

MHz

4.75V < Vdd < 5.25V

Maximum Frequency, Enable Input

–

–

24.96

MHz

Dead Band

Kill Pulse Width:

Asynchronous Restart Mode

20

–

–

ns

Synchronous Restart Mode

50

a

–

–

ns

Disable Mode

50

a

–

–

ns

Maximum Frequency

–

–

24.96

MHz

4.75V < Vdd < 5.25V

CRCPRS
(PRS Mode)

Maximum Input Clock Frequency

–

–

24.96

MHz

4.75V < Vdd < 5.25V

CRCPRS
(CRC Mode)

Maximum Input Clock Frequency

–

–

24.96

MHz

SPIM

Maximum Input Clock Frequency

–

–

4.1

MHz

Maximum data rate at 4.1 MHz 
due to 2 x over clocking.

SPIS

Maximum Input Clock Frequency

–

–

2.05

MHz

Width of SS_ Negated Between Transmissions

50

a

–

–

ns

Transmitter

Maximum Input Clock Frequency

–

–

8.2

MHz

Maximum data rate

 

at 3.08 

MHz due to 8 x over clocking.

Receiver

Maximum Input Clock Frequency

–

16

24.96

MHz

Maximum data rate

 

at 3.08 

MHz due to 8 x over clocking.