Fujitsu FR81S Manual Do Utilizador
CHAPTER 39: RAMECC
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RAMECC
FUJITSU SEMICONDUCTOR CONFIDENTIAL
11
4.5. ECC False Error Generation Control Register XBS
RAM : EFECRX
The bit configuration of the ECC false error generation control register XBS RAM is shown.
The ECC false error generation control register (EFECRX) specifies each false error by its byte position
and its bit position where the false error is generated.
EFECRX : Address 2409
H
(Access : Byte, Half-word, Word)
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
Reserved
FERR
Initial value
0
0
0
0
0
0
0
0
Attribute
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R,W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
EY7
EY6
EY5
EY4
EY3
EY2
EY1
EY0
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EI7
EI6
EI5
EI4
EI3
EI2
EI1
EI0
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit23 to bit17] Reserved
Always write "0" to these bits.
[bit16] FERR : False error generation enable bit
FERR
Function
0
False (Pseudo) ECC error generation disable
1
False (Pseudo) ECC error generation enable
This bit enables a false (pseudo) ECC error for XBS RAM.
"0": Prohibits a false (pseudo) ECC error. (Normal operation)
Also, writing "0" from software is ignored.
"1": Enables a false (pseudo) ECC error.
When this bit is set to "1", the following operation sequence is automatically performed.
1. Start writing data including an intentional error to the address specified by EFEARX following EY7 to
EY0, EI7 to EI0.
2. Read the same address and detect ECC error.
3. Clear this bit to “0”.
MB91520 Series
MN705-00010-1v0-E
1302