Fujitsu FR81S Manual Do Utilizador
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
7. Operation of LIN Interface (v2.1)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
275
Overview of pseudo LIN bus error test mode
The pseudo LIN bus error test is executed by the self-check of the master/slave who transmits data. A
pseudo LIN bus error cannot be detected by master/slave who receives the data.
Figure 7-22 Outline of pseudo LIN bus error test mode
Please set the LIN bus error pseudo trouble setting bit by the method of starting the pseudo error test mode
to start the pseudo LIN bus error test mode (LAMERT:LBSERT=1). The start of the pseudo LIN bus error
test mode operates as follows.
⋅
Master
Sync Field, ID Field, data, and checksum are transmitted.
Reception data is reversed according to the timing of the stop bit at time to which LIN bus error pseudo
trouble was set (LAMERT:LBSERT=1), the LIN bus error is generated when self-checking it, and "1" is set
to flag bit (LAMESR: LBSER).
⋅
Slave
Data and checksum are transmitted.
Reception data is reversed according to the timing of the stop bit at time to which LIN bus error pseudo
trouble was set (LAMERT:LBSERT=1), the LIN bus error is generated when self-checking it, and "1" is set
to flag bit (LAMESR: LBSER).
The LIN bus error is generated until the pseudo LIN bus error test mode setting is released
(LAMESR:LBSER=0).
Note:
The transmission/reception processing of the header/response part of the assist mode stops by LIN bus error
detection (LAMESR:LBSER=0).
SIN
SOUT
MPU
(header/response transmission node)
Transceiver
Transmission
data
Reception data
(self-check)
LIN bus error
Generation object
Transceiver
SIN
SOUT
MPU
(header/response reception node)
Reception data
LIN bus error
No generation object
： Route for pseudo error
： Off the subject route for pseudo error
： Off the subject route for pseudo error
Invert of Sync
Field,
ID Field,
data,
Checksum data
MB91520 Series
MN705-00010-1v0-E
1588