Fujitsu FR81S Manual Do Utilizador
CHAPTER 44: 12-BIT A/D CONVERTER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 12-BIT A/D CONVERTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
22
4.1.1. Analog Input Enable Register : ADER
The bit configuration of the analog input enable register is shown.
The analog input enable register (ADERH0, ADERL0, ADERL1) controls the analog input.
ADERH0: Address 04AC
H
(Access: Byte, Half-word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ADE31
ADE30
ADE29
ADE28
ADE27
ADE26
ADE25
ADE24
Initial value
1
1
1
1
1
1
1
1
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ADE23
ADE22
ADE21
ADE20
ADE19
ADE18
ADE17
ADE16
Initial value
1
1
1
1
1
1
1
1
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADERL0: Address 04AE
H
(Access: Byte, Half-word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ADE15
ADE14
ADE13
ADE12
ADE11
ADE10
ADE9
ADE08
Initial value
1
1
1
1
1
1
1
1
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ADE07
ADE06
ADE05
ADE04
ADE03
ADE02
ADE01
ADE00
Initial value
1
1
1
1
1
1
1
1
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit15 to bit0] ADE31 to ADE0 : Analog Input Enable Bits
ADE31 to ADE0
Function
0
Analog input enable
1
Analog input disable
The analog input pin is controlled.
If these bit are "0", the analog input is disabled.
If these bit are "1", the analog input is enabled.
Note:
This register is a key code target register. Key code setting is required for writing. For the setting method,
refer to sections "KEY CoDe Register : KEYCDR" and “key code register function settings” in “chapter I/O
PORTS”. In addition, word access to this register is disabled.
MB91520 Series
MN705-00010-1v0-E
1825