Fujitsu FR81S Manual Do Utilizador
CHAPTER 17: PPG
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: PPG
FUJITSU SEMICONDUCTOR CONFIDENTIAL
20
4.2. PPG Cycle Setting Register : PCSR0 to PCSR47
The bit configuration of the PPG cycle setting register is shown.
The PPG cycle setting register (PCSR) specifies the cycle of the PPG output waveform.
PPG cycle setting register (PCSR): Address Base_addr + 02
H
(Access:
Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
D14
D13
D12
D11
D10
D9
D8
Initial value
X
X
X
X
X
X
X
X
Attribute
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
Initial value
X
X
X
X
X
X
X
X
Attribute
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
R1,W
[bit15 to bit0] D15 to D0 : PPG cycle setting bits
D15 to D0
Function
Cycle of the PPG output waveform
The PPG cycle setting register has a buffer.
Data transfer from the buffer to the counter occurs automatically when a borrow occurs on the counter.
Be sure to set the PPG duty setting register (PDUT) after the PPG cycle setting register is rewritten.
Note: These bits are write-only.
Notes:
⋅
If the PPG output waveform selection bit (PCN.OWFS)="0" (Normal Wave Form) is selected, the
waveform is output at the cycle of a set value of PPG cycle setting register.
⋅
If the PPG output waveform selection bit (PCN.OWFS)=1 (Center Aligned Wave Form) is selected, the
waveform is output at twice the cycle of a set value of PPG cycle setting register.
⋅
Be sure to access this register by the word (16-bit) format. If the byte is accessed to this register, the
value is not written at an upper and lower bit position.
MB91520 Series
MN705-00010-1v0-E
561