Fujitsu FR81S Manual Do Utilizador
CHAPTER 19: BASE TIMER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
36
[bit2] EDIR (EnD Interrupt Register) : Measurement completion interrupt request flag bit
This bit indicates that the measurement of the 16/32-bit PWC timer is completed. When this bit is "1" and the
EDIE bit is set to "1", a measurement completion interrupt request is generated. This bit is cleared when the
measurement result (BTxDTBF) is read out.
[bit0] OVIR (OVerflow Interrupt Register) : Overflow interrupt request flag bit
This bit indicates that the up counter value has changed from "FFFF
H
" to "0000
H
" and an overflow occurred.
When this bit is "1" and the OVIE bit is set to "1", an overflow interrupt request is generated. This bit is
cleared when "0" is written.
EDIR/OVIR
Read
Write
0
Measurement completion/overflow has
not been occurred.
(EDIR) No effect on the operation.
(OVIR) This bit is cleared.
1
Measurement completion/overflow has
been occurred.
No effect on the operation.
MB91520 Series
MN705-00010-1v0-E
669