Fujitsu FR81S Manual Do Utilizador
CHAPTER 19: BASE TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
64
Note
:
⋅
The output method and output destination of the waveform (TOUT signal) from the 16-bit PWM timer
depend on the following settings:
⋅
Base timer I/O mode
⋅
TIOA0, TIOA1 pin functions
Interrupt Generation Timing
The 16-bit PPG timer can generate an interrupt request in one of the following events:
⋅
An activation trigger is detected.
⋅
The value of the 16-bit down counter matches the value of the base timer x duty setting register
(BTxPDUT)
⋅
When an underflow occurs:
An example of interrupt request generation timing using the following settings is shown below.
⋅
Value of the cycle setting register (BTxPCSR) = 0003
H
⋅
Value of the duty setting register (BTxPDUT) = 0001
H
Figure 5-15 Interrupt Request Generation Timing Chart
XXXX
H
0003
H
0002
H
0000
H
0001
H
0002
H
0003
H
Activation trigger
Load
Count clock
Counter value
PWM output
waveform
Interrupt request
Activation edge
trigger interrupt
request (TGIR bit)
Duty match
interrupt request
(DTIR bit)
Underflow
interrupt request
(UDIR bit)
2T to 3T (external activation trigger)
MB91520 Series
MN705-00010-1v0-E
697