Fujitsu FR81S Manual Do Utilizador
CHAPTER 22: 32-BIT OUTPUT COMPARE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT OUTPUT COMPARE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
12
4.3. Compare Register : OCCP
The bit configuration of the compare register is shown below.
These registers set the values to be compared with the 32-bit free-run timer count value.
x: Channel number 6, 8, and 10.
y: Channel number 7, 9, and 11.
OCCPx (Output compare x): Address Base_addr+00
H
(Access: Word)
OCCPy (Output compare y): Address Base_addr+04
H
(Access: Word)
bit31
32Bit
bit0
OP[31:0]
Initial value 0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
Attribute
R/W
⋅
The compare registers OCCP is compared with the count value of free-run timer (TCDT).
⋅
When the OCCP register values correspond to the 32-bit free-run timer value, a compare signal is
generated and an output compare interrupt flag is set. The compare value is reflected after the write
instruction is completed. Therefore, the compare value change during operation might generate an
interrupt twice per one free-run counting if the newly written compare value is larger than the previous
compare value.
⋅
In addition, when the corresponding OCU of the port function register (PFR) is set and output is enabled,
the output level corresponding to the compare register is changed.
⋅
For access to this register, use a word access instruction.
MB91520 Series
MN705-00010-1v0-E
849