Fujitsu FR81S Manual Do Utilizador
CHAPTER 17: PPG
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: PPG
FUJITSU SEMICONDUCTOR CONFIDENTIAL
43
Setting and operation procedure:
(1) Writing of PCSR (cycle value)
(2) Writing of PDUT (duty value) and transferring cycle value to the buffer (cycle value)
(3) Enabling of PPG operation
(4) Activation trigger generation
(5) Loading of the [(Cycle value) × 2 + 1] to the down count value (PTMR) and the duty value to the
buffer (duty value) and the buffer (duty value end point)
Duty value
(Output level inversion timing) = (Duty value + Cycle value + 1)
Duty value end point (Output level clear timing)
= (Cycle value - Duty value - 1)
(6) Rewriting of PDUT (duty value) and transferring cycle value to the buffer (cycle value)
(7) Counter decrement
(8) The down counter matches the duty value (output level inversion timing)
(9) Output level inversion at the PPG pin
(10) Counter decrement
(11) The down counter matches the duty value end point (output level clear timing)
(12) Clearing of PPG pin output level (restoration to normal state)
(13) Counter decrement
(14) Counter borrow occurrence
(15) Clearing of PPG pin output level (restoration to normal state)
(16) Reloading of the [(Cycle value) × 2 + 1] to the down count value (PTMR) and the duty value to the
buffer (duty value) and the buffer (duty value end point)
(17) Repetition of steps (7) to (16)
Calculation formulas:
⋅
Cycle = {(Cycle value (PCSR) + 1) × 2} × Count clock
⋅
Duty = {(Duty value (PDUT) + 1) × 2} × Count clock
⋅
Time to pulse output = {Cycle value (PCSR) - Duty value (PDUT)} × Count clock
MB91520 Series
MN705-00010-1v0-E
584