Motorola MVME5100 Manual Do Utilizador
Multi-Processor Interrupt Controller (MPIC)
http://www.motorola.com/computer/literature
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Program Visible Registers
These are the registers that software can access. They are described in
detail in the MPIC Registers section.
detail in the MPIC Registers section.
Interrupt Pending Register (IPR)
The interrupt signals to MPIC are qualified and synchronized to the clock
by the IPR. If the interrupt source is internal to the Hawk ASIC or external
with their Sense bit = 0 (edge sensitive), a bit is set in the IPR. That bit is
cleared when the interrupt associated with that bit is acknowledged. If the
interrupt source is external and level activated, the output from the IPR is
not negated until the level into the IPR is negated.
by the IPR. If the interrupt source is internal to the Hawk ASIC or external
with their Sense bit = 0 (edge sensitive), a bit is set in the IPR. That bit is
cleared when the interrupt associated with that bit is acknowledged. If the
interrupt source is external and level activated, the output from the IPR is
not negated until the level into the IPR is negated.
Externally sourced interrupts are qualified based upon their Sense and/or
Pol bits in the Vector-Priority register. IPI and Timer Interrupts are
generated internally to the Hawk ASIC and are qualified by their
Destination bit. Since the internally generated interrupts use direct delivery
mode with multicast capability, there are two bits in the IPR, one for each
processor, associated with each IPI and Timer interrupt source.
Pol bits in the Vector-Priority register. IPI and Timer Interrupts are
generated internally to the Hawk ASIC and are qualified by their
Destination bit. Since the internally generated interrupts use direct delivery
mode with multicast capability, there are two bits in the IPR, one for each
processor, associated with each IPI and Timer interrupt source.
The MASK bits from the Vector-Priority registers are used to qualify the
output of the IPR. Therefore, if an interrupt condition is detected when the
MASK bit is set, that interrupt will be requested when the MASK bit is
lowered.
output of the IPR. Therefore, if an interrupt condition is detected when the
MASK bit is set, that interrupt will be requested when the MASK bit is
lowered.
Interrupt Selector (IS)
There is a Interrupt Selector (IS) for each processor. The IS receives
interrupt requests from the IPR. If the interrupt requests are from an
external source, they are qualified by the destination bit for that interrupt
and processor. If they are from an internal source, they have been qualified.
The output of the IS will be the highest priority interrupt that has been
qualified. This output is the priority of the selected interrupt and its source
identification. The IS will resolve an interrupt request in two PHB clock
ticks.
interrupt requests from the IPR. If the interrupt requests are from an
external source, they are qualified by the destination bit for that interrupt
and processor. If they are from an internal source, they have been qualified.
The output of the IS will be the highest priority interrupt that has been
qualified. This output is the priority of the selected interrupt and its source
identification. The IS will resolve an interrupt request in two PHB clock
ticks.
The IS also receives a second set of inputs from the ISR. During the End
Of Interrupt cycle, these inputs are used to select which bits are to be
cleared in the ISR.
Of Interrupt cycle, these inputs are used to select which bits are to be
cleared in the ISR.