Motorola MVME5100 Manual Do Utilizador

List of Figures

Figure 1-1. MVME5100 Block Diagram ...................................................................1-3
Figure 1-2. VMEbus Master Mapping .....................................................................1-18
Figure 2-1. Hawk PCI Host Bridge Block Diagram ..................................................2-3
Figure 2-2. PPC to PCI Address Decoding................................................................2-6
Figure 2-3. PPC to PCI Address Translation .............................................................2-7
Figure 2-4. PCI to PPC Address Decoding..............................................................2-20
Figure 2-5. PCI to PPC Address Translation ...........................................................2-21
Figure 2-6. PCI Spread I/O Address Translation .....................................................2-31
Figure 2-7. Big-to-Little-Endian Data Swap ...........................................................2-39
Figure 2-8. Serial Mode Interrupt Scan ...................................................................2-52
Figure 2-9. MPIC Block Diagram ...........................................................................2-58
Figure 3-1. Hawk Used with Synchronous DRAM in a System ..............................3-2
Figure 3-2. Hawk’s System Memory Controller Internal Data Paths ........................3-3
Figure 3-3. Overall SDRAM Connections (4 Blocks using Register Buffers) ..........3-4
Figure 3-4. Hawk’s System Memory Controller Block Diagram ..............................3-5
Figure 3-5. Programming Sequence for I2C Byte Write .........................................3-24
Figure 3-6. Programming Sequence for I2C Random Read ....................................3-26
Figure 3-7. Programming Sequence for I2C Current Address Read .......................3-28
Figure 3-8. Programming Sequence for I2C Page Write .........................................3-30
Figure 3-9. Programming Sequence for I2C Sequential Read.................................3-33
Figure 3-10. Read/Write Check-bit Data Paths........................................................3-47
Figure 4-1. Big-Endian Mode ....................................................................................4-7
Figure 4-2. Little-Endian Mode .................................................................................4-8