Motorola MVME5100 Manual Do Utilizador
Registers
http://www.motorola.com/computer/literature
2-99
2
PCI Command/ Status Registers
The Command Register (COMMAND) provides coarse control over the
PHB ability to generate and respond to PCI cycles. The bits within the
COMMAND register are defined as follows:
PHB ability to generate and respond to PCI cycles. The bits within the
COMMAND register are defined as follows:
IOSP
IO Space Enable. If set, the PHB will respond to PCI I/O
accesses when appropriate. If cleared, the PHB will not
respond to PCI I/O space accesses.
accesses when appropriate. If cleared, the PHB will not
respond to PCI I/O space accesses.
MEMSP
Memory Space Enable. If set, the PHB will respond to
PCI memory space accesses when appropriate. If cleared,
the PHB will not respond to PCI memory space accesses.
PCI memory space accesses when appropriate. If cleared,
the PHB will not respond to PCI memory space accesses.
MSTR
Bus Master Enable. If set, the PHB may act as a master
on PCI. If cleared, the PHB may not act as a PCI Master.
on PCI. If cleared, the PHB may not act as a PCI Master.
PERR
Parity Error Response. If set, the PHB will check parity
on all PCI transfers. If cleared, the PHB will ignore any
parity errors that it detects and continue normal operation.
on all PCI transfers. If cleared, the PHB will ignore any
parity errors that it detects and continue normal operation.
SERR
System Error Enable. This bit enables the SERR_ output
pin. If clear, the PHB will never drive SERR_. If set, the
PHB will drive SERR_ active when a system error is
detected.
pin. If clear, the PHB will never drive SERR_. If set, the
PHB will drive SERR_ active when a system error is
detected.
Offset
$04
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
STATUS
COMMAND
RC
V
P
E
SI
GS
E
RC
V
M
A
RC
V
T
A
SI
G
T
A
SE
L
T
IM
1
SE
L
T
IM
0
DP
AR
FA
S
T
P
66M
SE
R
R
PE
R
R
MSTR
MEMS
P
IOS
P
Operation
R/C
R/C
R/C
R/C
R/C
R
R
R/C
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/
W
R
R/
W
R
R
R
R/
W
R/
W
R/
W
Reset
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0