FIC M296 Manual Do Utilizador
Troubleshooting and Repair
Beep codes for system board errors
Table 6-3 (a)
BIOS Beep Codes
Beep
Code
Diagnostic
Code
Description Test
Performed
none 01h
CPU registers test in
progress or failure
progress or failure
Pattern test of most of the 16-bit CPU
registers. Failure will result in a system
halt.
registers. Failure will result in a system
halt.
1-1-3 02h
CMOS write/read test in
progress or failure.
progress or failure.
Rolling ones test in the shutdown byte
(offset 0Eh) of the CMOS RAM. Failure
will result in a system halt.
(offset 0Eh) of the CMOS RAM. Failure
will result in a system halt.
1-1-4 03h
ROM BIOS checksum test in
progress or failure.
progress or failure.
The range of ROM that includes the
BIOS is checksummed. Failure will result
in a system halt.
BIOS is checksummed. Failure will result
in a system halt.
1-2-1 04h
Programmable interval timer
0 test in progress or failure.
0 test in progress or failure.
Over a period of time, the current count
values in timer 0 are read and
accumulated by ORing them into the
values read so far. It is expected that
during the time period, all bits will be set.
Failure will result in a system halt.
values in timer 0 are read and
accumulated by ORing them into the
values read so far. It is expected that
during the time period, all bits will be set.
Failure will result in a system halt.
1-2-2 05h
DMA channel 0 address and
count register test in progress
or failure.
count register test in progress
or failure.
Rolling ones and rolling zeros test of the
address and count registers of DMA
channel 0. Failure will result in a system
halt.
address and count registers of DMA
channel 0. Failure will result in a system
halt.
1-2-3 06h
DMA page register write/read
test in progress of failure.
test in progress of failure.
Pattern test of DMA page registers.
Failure will result in a system halt.
Failure will result in a system halt.
1-3-1 08h
RAM refresh verification test
in progress or failure.
in progress or failure.
Over a period of time, the refresh bit (bit
4) in port 60h is read and tested. The
refresh bit should toggle from 0 to 1, then
1 to 0 within the time period. Failure will
result in system halt.
4) in port 60h is read and tested. The
refresh bit should toggle from 0 to 1, then
1 to 0 within the time period. Failure will
result in system halt.
none 09h
First 64K RAM test in
progress.
progress.
No specific test is performed - just
indicates that the test is beginning.
indicates that the test is beginning.
1-3-3 0Ah
First 64K RAM chip or data
line failure, multi-bit.
line failure, multi-bit.
The first 64K of RAM is tested with a
rolling ones test and a pattern test. If any
of the pattern tests fail, then the BIOS
reports that multiple data bits failure.
Failure results in a system halt.
rolling ones test and a pattern test. If any
of the pattern tests fail, then the BIOS
reports that multiple data bits failure.
Failure results in a system halt.
1-4-2
0Dh
Parity failure first 64K RAM
At the completion of the rolling ones and
pattern tests of the first 64K, the BIOS
checks the parity error bits (bits 7 and 6)
of port 60h. Failure results in a system
halt.
pattern tests of the first 64K, the BIOS
checks the parity error bits (bits 7 and 6)
of port 60h. Failure results in a system
halt.
FIC M295 / M296 Service Manual 6-5