Samsung S3C2440A Manual Do Utilizador
S3C2440A RISC MICROPROCESSOR
CAMERA INTERFACE
23-1
23
CAMERA INTERFACE
OVERVIEW
This chapter will explain the specification and defines the camera interface. CAMIF (CAMera InterFace) within the
S3C2440A consists of 7 parts – pattern mux, capturing unit, preview scaler, codec scaler, preview DMA,
codec DMA, and SFR. The CAMIF supports ITU-R BT.601/656 YCbCr 8-bit standard. Maximum input size is
4096x4096 pixels (2048x2048 pixels for scaling) and two scalers exist. Preview scaler is dedicated to generate
smaller size image like PIP (Picture In Picture) and codec scaler is dedicated to generate codec useful image like
plane type YCbCr 4:2:0 or 4:2:2. Two master DMAs can do mirror and rotate the captured image for mobile
environments. These features are very useful in folder type cellular phones and the test pattern generated can be
useful in calibration of input sync signals as CAMHREF, CAMVSYNC. Also, video sync signals and pixel clock
polarity can be inverted in the CAMIF side by using register setting.
S3C2440A consists of 7 parts – pattern mux, capturing unit, preview scaler, codec scaler, preview DMA,
codec DMA, and SFR. The CAMIF supports ITU-R BT.601/656 YCbCr 8-bit standard. Maximum input size is
4096x4096 pixels (2048x2048 pixels for scaling) and two scalers exist. Preview scaler is dedicated to generate
smaller size image like PIP (Picture In Picture) and codec scaler is dedicated to generate codec useful image like
plane type YCbCr 4:2:0 or 4:2:2. Two master DMAs can do mirror and rotate the captured image for mobile
environments. These features are very useful in folder type cellular phones and the test pattern generated can be
useful in calibration of input sync signals as CAMHREF, CAMVSYNC. Also, video sync signals and pixel clock
polarity can be inverted in the CAMIF side by using register setting.
FEATURES
•
ITU-R BT. 601/656 8-bit mode external interface support
•
DZI (Digital Zoom In) capability
•
Programmable polarity of video sync signals
•
Max. 4096 x 4096 pixel input support without scaling (2048 x 2048 pixel input support with scaling)
•
Max. 4096 x 4096 pixel output support for CODEC path
•
Max. 640 x 480 pixel output support for PREVIEW path
•
Image mirror and rotation (X-axis mirror, Y-axis mirror, and 180
°
rotation)
•
PIP and codec input image generation (RGB 16/24-bit format and YCbCr 4:2:0/4:2:2 format)
SIGNAL DESCRIPTION
Table 23-1. Camera interface signal description
Name
I/O
Active
Description
CAMPCLK
I
–
Pixel Clock, driven by the Camera processor
CAMVSYNC
I
H/L
Frame Sync, driven by the Camera processor
CAMHREF
I
H/L
Horizontal Sync, driven by the Camera processor
CAMDATA[7:0]
I
–
Pixel Data driven by the Camera processor
CAMCLKOUT
O
–
Master Clock to the Camera processor
CAMRESET
O
H/L
Software Reset or Power down to the Camera processor
Note: I/O direction is on the AP side. I: input, O: output