ARM NIC-301 Manual Do Utilizador

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Programmers Model 
ARM DDI 0397G
Copyright © 2006-2010 ARM. All rights reserved.
3-6
ID031010
Non-Confidential
Table 3-3 shows the registers that exist for each AMIB.
0x044
-
-
-
-
Reserved.
0x100
-
-
-
-
Reserved.
0x104
-
-
-
-
Reserved.
0x108
RW
2
0
fn_mod_iss
Issuing functionality modification register.
Issuing override, sets block issuing capability to one transaction and 
you can configure the bits as follows:
Read issuing, 
read_iss_override
.
Write issuing, 
write_iss_override
.
0x10C
-
-
-
-
Reserved
0x110
-
-
-
-
Reserved
a. The reset value is initialized to the tidemark value that you set in the configuration GUI in AMBA Designer (ADR-301).
Table 3-2 Registers for each IB (continued)
Address
offset
Type
Width
Reset
value
Name
Description
Table 3-3 Registers for each AMIB
Address
offset
Type
Width
Reset
value
Name
Description
0x000
-
-
-
-
Reserved.
0x004
-
-
-
-
Reserved.
0x008
RW
2
0
fn_mod_bm_iss
Bus matrix issuing functionality modification register. This register is 
only present if the block is connected directly to a switch.
This register sets the issuing capability of the preceding switch arbitration 
scheme to 1. You can configure the register bits as follows:
Read issuing, 
read_iss_override
.
Write issuing, 
write_iss_override
.
0x00C
-
-
-
-
Reserved.
0x020
RW
3
4
Sync_mode
This register is only available if you have a FIFO for all channels. You can 
configure the register bits to create different clock domain boundaries as 
follows:
sync 1:1.
sync n:1.
sync 1:n.
sync m:n.
async.
reserved.
reserved.
reserved.
0x024
RW
1
0
fn_mod2
Bypass merge. This register is only present if upsizing or downsizing. See 
Upsizing data width function on page 2-12 and Downsizing data width 
function
 on page 2-14.
0x028
-
-
-
-
Reserved.