Intel 253668-032US Manual Do Utilizador

10-32   Vol. 3

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

The setup information that can be specified in the registers of the LVT table is as 
follows:
Vector

Interrupt vector number.

Specifies the type of interrupt to be sent to the processor. Some 

delivery modes will only operate as intended when used in 
conjunction with a specific trigger mode. The allowable delivery 
modes are as follows:

Delivers the interrupt specified in the vector 
field.

Delivers an SMI interrupt to the processor 
core through the processor’s local SMI signal 
path. When using this delivery mode, the 
vector field should be set to 00H for future 
compatibility.

Delivers an NMI interrupt to the processor. 
The vector information is ignored. 

Delivers an INIT request to the processor 
core, which causes the processor to perform 
an INIT. When using this delivery mode, the 
vector field should be set to 00H for future 
compatibility.

111 (ExtINT) Causes the processor to respond to the in-

terrupt as if the interrupt originated in an 
externally connected (8259A-compatible) 
interrupt controller. A special INTA bus cycle 
corresponding to ExtINT, is routed to the ex-
ternal controller. The external controller is 
expected to supply the vector information. 
The APIC architecture supports only one Ex-
tINT source in a system, usually contained in 
the compatibility bridge.

Delivery Status (Read Only) 

Indicates the interrupt delivery status, as follows:

There is currently no activity for this inter-
rupt source, or the previous interrupt from 
this source was delivered to the processor 
core and accepted.

1 (Send Pending) 

Indicates that an interrupt from this source 
has been delivered to the processor core, 
but has not yet been accepted (see Section 
10.6.5, “Local Interrupt Acceptance”).