Texas Instruments TMS320DM355 Manual Do Utilizador
www.ti.com
PRODUCT PREVIEW
2.4.2
Image Data Output - Video Processing Back End (VPBE)
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007
Table 2-5. CCD Controller/Video Input Terminal Functions (continued)
TERMINAL
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
NAME
NO.
Standard CCD Analog Front End (AFE): Raw[05]
•
YCC 16-bit: Time multiplexed between chroma: Y[05]
YIN5/
PD
M5
I/O/Z
•
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO091
V
DD_VIN
multiplexed between luma and chroma of the upper channel. Y/CB/CR[05]
GIO: GIO[091]
Standard CCD Analog Front End (AFE): Raw[04]
•
YCC 16-bit: Time multiplexed between chroma: Y[04]
YIN4/
PD
P3
I/O/Z
•
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO090
V
DD_VIN
multiplexed between luma and chroma of the upper channel. Y/CB/CR[04]
GIO: GIO[090]
Standard CCD Analog Front End (AFE): Raw[03]
•
YCC 16-bit: Time multiplexed between chroma: Y[03]
YIN3/
PD
R3
I/O/Z
•
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO089
V
DD_VIN
multiplexed between luma and chroma of the upper channel. Y/CB/CR[03]
GIO: GIO[089]
Standard CCD Analog Front End (AFE): Raw[02]
•
YCC 16-bit: Time multiplexed between chroma: Y[02]
YIN2/
PD
P4
I/O/Z
•
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO088
V
DD_VIN
multiplexed between luma and chroma of the upper channel. Y/CB/CR[02]
GIO: GIO[088]
Standard CCD Analog Front End (AFE): Raw[01]
•
YCC 16-bit: Time multiplexed between chroma: Y[01]
YIN1/
PD
P2
I/O/Z
•
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO087
V
DD_VIN
multiplexed between luma and chroma of the upper channel. Y/CB/CR[01]
GIO: GIO[087]
Standard CCD Analog Front End (AFE): Raw[00]
•
YCC 16-bit: Time multiplexed between chroma: Y[00]
YIN0/
PD
P5
I/O/Z
•
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO086
V
DD_VIN
multiplexed between luma and chroma of the upper channel. Y/CB/CR[00]
GIO: GIO[086]
Horizontal synchronization signal that can be either an input (slave mode) or an
CAM_HD/
PD
N5
I/O/Z
output (master mode). Tells the CCDC when a new line starts.
GIO085
V
DD_VIN
GIO: GIO[085]
Vertical synchronization signal that can be either an input (slave mode) or an output
CAM_VD
PD
R4
I/O/Z
(master mode). Tells the CCDC when a new frame starts.
GIO084
V
DD_VIN
GIO: GIO[084]
Write enable input signal is used by external device (AFE/TG) to gate the DDR
output of the CCDC module. Alternately, the field identification input signal is used
output of the CCDC module. Alternately, the field identification input signal is used
CAM_WEN
PD
by external device (AFE/TG) to indicate which of two frames is input to the CCDC
_FIELD\
R5
I/O/Z
V
DD_VIN
module for sensors with interlaced output. CCDC handles 1- or 2-field sensors in
GIO083
hardware.
GIO: GIO[083]
GIO: GIO[083]
PCLK/
PD
Pixel clock input (strobe for lines C17 through Y10)
T3
I/O/Z
GIO082
V
DD_VIN
GIO: GIO[0082]
The Video Encoder/Digital LCD interface module in the video processing back end has an external signal
interface for digital image data output as described in
interface for digital image data output as described in
and
.
The digital image data output signals support multiple functions / interfaces, depending on the display
mode selected. The following table describes these modes. Parallel RGB mode with more than RGB565
signals requires enabling pin multiplexing to support (i.e., for RGB666 mode).
mode selected. The following table describes these modes. Parallel RGB mode with more than RGB565
signals requires enabling pin multiplexing to support (i.e., for RGB666 mode).
Device Overview
15