Renesas R5S72625 Manual Do Utilizador

 

Section 26   USB 2.0 Host/Function Module 

R01UH0134EJ0400  Rev. 4.00  

 

Page 1359 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

6 

USBRST 

0 

R/W 

Bus Reset Output 

Controls the USB bus reset signal output when the 
host controller function is selected. 

0: USB bus reset signal is not output. 

1: USB bus reset signal is output. 

When the host controller function is selected, setting 
this bit to 1 allows this module to drive the USB port 
to SE0 to reset the USB bus. Here, this module 
performs the reset handshake protocol if the HSE bit 
is 1. 

This module continues outputting SE0 while 
USBRST is 1 (until 0 is written to USBRST). 
USBRST should be 1 (= USB bus reset period) for 
the time defined by USB Specification 2.0. 

Writing 1 to this bit during communication (UACT = 
1) or during the resume process (RESUME = 1) 
prevents this module from starting the USB bus reset 
process until both UACT and RESUME become 0. 

Write 1 to the UACT bit simultaneously with the end 
of the USB bus reset process (writing 0 to USBRST). 

This bit should be set to 0 if the function controller 
function is selected. 

5 RESUME 

0  R/W 

Resume 

Output 

Controls the resume signal output when the host 
controller function is selected. 

0: Resume signal is not output. 

1: Resume signal is output. 

Setting this bit to 1 allows this module to drive the 
port to the K-state and output the resume signal. 

This module continues outputting K-state while 
RESUME is 1 (until 0 is written to RESUME). 
RESUME should be 1 (= resume period) for the time 
defined by USB Specification 2.0. 

This bit should be set to 1 in the suspended state. 

Write 1 to the UACT bit simultaneously with the end 
of the resume process (writing 0 to RESUME).  

This bit should be set to 0 if the function controller 
function is selected.