Renesas R5S72625 Manual Do Utilizador
Section 33 Power-Down Modes
R01UH0134EJ0400 Rev. 4.00
Page 1771 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
State*
1
Power-
Down
Mode
Transition
Conditions
Clock
Pulse
Genera-
tor
CPU
CPU
Register
High-
Speed
On-Chip
RAM
Cash
Memory
Large-
Capacity
On-Chip
RAM
(for Data
Retention)
On-Chip
Peripheral
Modules
Realtime
Clock
Power
supply
External
Memory
Canceling
Procedure
Module
standby
mode
Set the MSTP
bits in
STBCR2 to
STBCR8 to 1
Running Running Held
Running
Running
Specified
module
halted
Halted Running Auto-
refresh
Clear MSTP
bit to 0
Power-on
reset (only for
the user
debugging
interface and
direct memory
access
controller)
Notes: 1. The pin state is retained or set to high impedance. For details, see appendix A, Pin
States.
2. The realtime clock operates when the START bit in the RCR2 register is set to 1. For
details, see section 14, Realtime Clock. When deep standby mode is canceled by a
power-on reset, the running state cannot be retained. Make the initial setting for the
realtime clock again.
power-on reset, the running state cannot be retained. Make the initial setting for the
realtime clock again.
3. Setting the bits RRAMKP3 to RRAMKP0 in the RRAMKP register to 1 enables to retain
the data in the corresponding area on the on-chip data-retention RAM during the
transition to deep standby. When the deep standby is canceled by a power-on reset,
the retained contents are initialized. RRAMKP3 and RRAMKP2 can be used only for
640-Kbyte version.
transition to deep standby. When the deep standby is canceled by a power-on reset,
the retained contents are initialized. RRAMKP3 and RRAMKP2 can be used only for
640-Kbyte version.
4. Deep standby mode can be canceled by an interrupt (NMI or realtime clock alarm
interrupt), a power-on reset, or change on the pins for canceling (PC8 to PC5,PG10 to
PG11, PJ3, and PJ1). Even when deep standby mode is canceled by a source other
than a reset, power-on reset exception handling is executed instead of interrupt
exception handling. PG10 to PG11 operates as pins for canceling only in 640-Kbyte
version.
PG11, PJ3, and PJ1). Even when deep standby mode is canceled by a source other
than a reset, power-on reset exception handling is executed instead of interrupt
exception handling. PG10 to PG11 operates as pins for canceling only in 640-Kbyte
version.
5. When software standby mode is canceled by a power-on reset, the retained contents
are initialized.
6. By setting the RAME bit in SYSCR1 or RAMWE bit in SYSCR2 to disable accesses,
contents in the high-speed on-chip RAM can be retained even when software standby
mode is canceled by a power-on reset.
mode is canceled by a power-on reset.
7. By setting the VRAME bit in SYSCR3 or VRAMWE bit in SYSCR4 to disable accesses,
contents in the large-capacity on-chip RAM (including on-chip data-retention RAM) can
be retained even when software standby mode is canceled by a power-on reset.
be retained even when software standby mode is canceled by a power-on reset.