Renesas R5S72625 Manual Do Utilizador

 
Section 7   Interrupt Controller 
 

Page 158 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

Figure 7.1 shows a block diagram. 

Direct memory access controller

USB 2.0 host/function module

Video display controller 3

Compare match timer

Bus state controller

Watchdog timer

Multi-function timer pulse unit 2

Motor control PWM timer

A/D converter

Serial sound interface

Renesas SPDIF interface

 I

2

C bus interface 3

Serial communication interface with FIFO

Serial I/O with FIFO

Renesas serial peripheral interface

Controller area network

IEBus

TM

 controller

CD-ROM decoder

NAND flash memory controller

SD host interface

Realtime clock

Sampling rate converter

Decompression unit

Priority

identifier

Com-
parator

Interrupt

request

SR

CPU

Bus 

interface

Module bus

P

er

ipher

al b

us

I3 I2 I1 I0

(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)

PINTER

IBCR

IPR01, PR02, 

IPR05 to IPR22

ICR0

ICR2

PIRR

IBNR

ICR1

IRQRR

PINT7 to PINT0

IRQ7 to IRQ0

NMI

IPR

ICR0:
ICR1:
ICR2:
IRQRR:
PINTER:
PIRR:
IBCR:
IBNR:
IPR01, IPR02, IPR05 to IPR22:

Interrupt control register 0
Interrupt control register 1
Interrupt control register 2
IRQ interrupt request register
PINT interrupt enable register
PINT interrupt request register
Bank control register
Bank number register
Interrupt priority registers 01, 02, 05 to 22

[Legend]

Interrupt controller

Input 

control