Renesas R5S72623 Manual Do Utilizador
Section 19 Serial I/O with FIFO
R01UH0134EJ0400 Rev. 4.00
Page 969 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Table 19.8 Conditions to Issue Transmit Request
TFWM2 to
TFWM0
TFWM0
Number of
Requested
Stages
Requested
Stages
Transmit Request Issued
Used Areas
000
1
There are sixteen stages of empty area.
Smallest
100
4
There are twelve or more stages of empty area.
101
8
There are eight or more stages of empty area.
110
12
There are four or more stages of empty area.
111
16
There is one or more stage of empty area.
Largest
Table 19.9 Conditions to Issue Receive Request
RFWM2 to
RFWM0
RFWM0
Number of
Requested Stages Receive Request Issued
Requested Stages Receive Request Issued
Used Areas
000
1
There is one or more stage of valid data.
Smallest
100
4
There are four stages of valid data or more.
101
8
There are eight stages of valid data or more.
110
12
There are twelve stages of valid data or more.
111
16
There are sixteen stages of valid data.
Largest
The number of stages of the FIFO is sixteen. Accordingly, an overflow error or underflow error
occurs if data area or empty area exceeds sixteen FIFO stages. The transfer request is canceled
when the above condition is not satisfied even if the FIFO is not empty or full.
occurs if data area or empty area exceeds sixteen FIFO stages. The transfer request is canceled
when the above condition is not satisfied even if the FIFO is not empty or full.
(3) Number of FIFOs
The usage state of the transmit FIFO and receive FIFO are indicated by the TFUA and FRUA bits
in the FIFO control register as below:
in the FIFO control register as below:
Transmit FIFO: The number of empty FIFO stages is indicated by the TFUA4 to TFUA0 bits
in SIFCTR.
Receive FIFO: The number of valid data stages is indicated by the RFUA4 to RFUA0 bits in
SIFCTR.
The above register contents indicate the possible data numbers that can be transferred by the CPU
or direct memory access controller.
or direct memory access controller.